1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright Intel Corporation (C) 2017. All Rights Reserved 4*c66ec88fSEmmanuel Vadot * 5*c66ec88fSEmmanuel Vadot * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip 6*c66ec88fSEmmanuel Vadot * 7*c66ec88fSEmmanuel Vadot * Adapted from altr,rst-mgr-a10.h 8*c66ec88fSEmmanuel Vadot */ 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H 11*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel Vadot /* Peripheral PHY resets */ 14*c66ec88fSEmmanuel Vadot #define A10SR_RESET_ENET_HPS 0 15*c66ec88fSEmmanuel Vadot #define A10SR_RESET_PCIE 1 16*c66ec88fSEmmanuel Vadot #define A10SR_RESET_FILE 2 17*c66ec88fSEmmanuel Vadot #define A10SR_RESET_BQSPI 3 18*c66ec88fSEmmanuel Vadot #define A10SR_RESET_USB 4 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel Vadot #define A10SR_RESET_NUM 5 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel Vadot #endif 23