1*5956d97fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*5956d97fSEmmanuel Vadot #ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ 3*5956d97fSEmmanuel Vadot #define __DT_BINDINGS_POWER_RK3568_POWER_H__ 4*5956d97fSEmmanuel Vadot 5*5956d97fSEmmanuel Vadot /* VD_CORE */ 6*5956d97fSEmmanuel Vadot #define RK3568_PD_CPU_0 0 7*5956d97fSEmmanuel Vadot #define RK3568_PD_CPU_1 1 8*5956d97fSEmmanuel Vadot #define RK3568_PD_CPU_2 2 9*5956d97fSEmmanuel Vadot #define RK3568_PD_CPU_3 3 10*5956d97fSEmmanuel Vadot #define RK3568_PD_CORE_ALIVE 4 11*5956d97fSEmmanuel Vadot 12*5956d97fSEmmanuel Vadot /* VD_PMU */ 13*5956d97fSEmmanuel Vadot #define RK3568_PD_PMU 5 14*5956d97fSEmmanuel Vadot 15*5956d97fSEmmanuel Vadot /* VD_NPU */ 16*5956d97fSEmmanuel Vadot #define RK3568_PD_NPU 6 17*5956d97fSEmmanuel Vadot 18*5956d97fSEmmanuel Vadot /* VD_GPU */ 19*5956d97fSEmmanuel Vadot #define RK3568_PD_GPU 7 20*5956d97fSEmmanuel Vadot 21*5956d97fSEmmanuel Vadot /* VD_LOGIC */ 22*5956d97fSEmmanuel Vadot #define RK3568_PD_VI 8 23*5956d97fSEmmanuel Vadot #define RK3568_PD_VO 9 24*5956d97fSEmmanuel Vadot #define RK3568_PD_RGA 10 25*5956d97fSEmmanuel Vadot #define RK3568_PD_VPU 11 26*5956d97fSEmmanuel Vadot #define RK3568_PD_CENTER 12 27*5956d97fSEmmanuel Vadot #define RK3568_PD_RKVDEC 13 28*5956d97fSEmmanuel Vadot #define RK3568_PD_RKVENC 14 29*5956d97fSEmmanuel Vadot #define RK3568_PD_PIPE 15 30*5956d97fSEmmanuel Vadot #define RK3568_PD_LOGIC_ALIVE 16 31*5956d97fSEmmanuel Vadot 32*5956d97fSEmmanuel Vadot #endif 33