1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2016 Glider bvba 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__ 6*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_POWER_R8A7790_SYSC_H__ 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot /* 9*c66ec88fSEmmanuel Vadot * These power domain indices match the numbers of the interrupt bits 10*c66ec88fSEmmanuel Vadot * representing the power areas in the various Interrupt Registers 11*c66ec88fSEmmanuel Vadot * (e.g. SYSCISR, Interrupt Status Register) 12*c66ec88fSEmmanuel Vadot */ 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA15_CPU0 0 15*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA15_CPU1 1 16*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA15_CPU2 2 17*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA15_CPU3 3 18*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA7_CPU0 5 19*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA7_CPU1 6 20*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA7_CPU2 7 21*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA7_CPU3 8 22*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA15_SCU 12 23*c66ec88fSEmmanuel Vadot #define R8A7790_PD_SH_4A 16 24*c66ec88fSEmmanuel Vadot #define R8A7790_PD_RGX 20 25*c66ec88fSEmmanuel Vadot #define R8A7790_PD_CA7_SCU 21 26*c66ec88fSEmmanuel Vadot #define R8A7790_PD_IMP 24 27*c66ec88fSEmmanuel Vadot 28*c66ec88fSEmmanuel Vadot /* Always-on power area */ 29*c66ec88fSEmmanuel Vadot #define R8A7790_PD_ALWAYS_ON 32 30*c66ec88fSEmmanuel Vadot 31*c66ec88fSEmmanuel Vadot #endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */ 32