1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * This header provides constants for Tegra pinctrl bindings. 4*c66ec88fSEmmanuel Vadot * 5*c66ec88fSEmmanuel Vadot * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 6*c66ec88fSEmmanuel Vadot * 7*c66ec88fSEmmanuel Vadot * Author: Laxman Dewangan <ldewangan@nvidia.com> 8*c66ec88fSEmmanuel Vadot */ 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H 11*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_PINCTRL_TEGRA_H 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel Vadot /* 14*c66ec88fSEmmanuel Vadot * Enable/disable for diffeent dt properties. This is applicable for 15*c66ec88fSEmmanuel Vadot * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, 16*c66ec88fSEmmanuel Vadot * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. 17*c66ec88fSEmmanuel Vadot */ 18*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_DISABLE 0 19*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_ENABLE 1 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_PULL_NONE 0 22*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_PULL_DOWN 1 23*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_PULL_UP 2 24*c66ec88fSEmmanuel Vadot 25*c66ec88fSEmmanuel Vadot /* Low power mode driver */ 26*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_LP_DRIVE_DIV_8 0 27*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_LP_DRIVE_DIV_4 1 28*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_LP_DRIVE_DIV_2 2 29*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_LP_DRIVE_DIV_1 3 30*c66ec88fSEmmanuel Vadot 31*c66ec88fSEmmanuel Vadot /* Rising/Falling slew rate */ 32*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_SLEW_RATE_FASTEST 0 33*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_SLEW_RATE_FAST 1 34*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_SLEW_RATE_SLOW 2 35*c66ec88fSEmmanuel Vadot #define TEGRA_PIN_SLEW_RATE_SLOWEST 3 36*c66ec88fSEmmanuel Vadot 37*c66ec88fSEmmanuel Vadot #endif 38