1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Device Tree constants for the Texas Instruments DP83867 PHY 4*c66ec88fSEmmanuel Vadot * 5*c66ec88fSEmmanuel Vadot * Author: Dan Murphy <dmurphy@ti.com> 6*c66ec88fSEmmanuel Vadot * 7*c66ec88fSEmmanuel Vadot * Copyright: (C) 2015 Texas Instruments, Inc. 8*c66ec88fSEmmanuel Vadot */ 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_TI_DP83867_H 11*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_TI_DP83867_H 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel Vadot /* PHY CTRL bits */ 14*c66ec88fSEmmanuel Vadot #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 15*c66ec88fSEmmanuel Vadot #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 16*c66ec88fSEmmanuel Vadot #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 17*c66ec88fSEmmanuel Vadot #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel Vadot /* RGMIIDCTL internal delay for rx and tx */ 20*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_250_PS 0x0 21*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_500_PS 0x1 22*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_750_PS 0x2 23*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_1_NS 0x3 24*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_1_25_NS 0x4 25*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_1_50_NS 0x5 26*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_1_75_NS 0x6 27*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_2_00_NS 0x7 28*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_2_25_NS 0x8 29*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_2_50_NS 0x9 30*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_2_75_NS 0xa 31*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_3_00_NS 0xb 32*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_3_25_NS 0xc 33*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_3_50_NS 0xd 34*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_3_75_NS 0xe 35*c66ec88fSEmmanuel Vadot #define DP83867_RGMIIDCTL_4_00_NS 0xf 36*c66ec88fSEmmanuel Vadot 37*c66ec88fSEmmanuel Vadot /* IO_MUX_CFG - Clock output selection */ 38*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 39*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 40*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 41*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 42*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 43*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 44*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 45*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 46*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 47*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 48*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA 49*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB 50*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_REF_CLK 0xC 51*c66ec88fSEmmanuel Vadot /* Special flag to indicate clock should be off */ 52*c66ec88fSEmmanuel Vadot #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF 53*c66ec88fSEmmanuel Vadot #endif 54