xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/mfd/stm32f4-rcc.h (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */
2*c66ec88fSEmmanuel Vadot /*
3*c66ec88fSEmmanuel Vadot  * This header provides constants for the STM32F4 RCC IP
4*c66ec88fSEmmanuel Vadot  */
5*c66ec88fSEmmanuel Vadot 
6*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H
7*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_MFD_STM32F4_RCC_H
8*c66ec88fSEmmanuel Vadot 
9*c66ec88fSEmmanuel Vadot /* AHB1 */
10*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOA	0
11*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOB	1
12*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOC	2
13*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOD	3
14*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOE	4
15*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOF	5
16*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOG	6
17*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOH	7
18*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOI	8
19*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOJ	9
20*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_GPIOK	10
21*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_CRC	12
22*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_BKPSRAM	18
23*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_CCMDATARAM	20
24*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_DMA1	21
25*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_DMA2	22
26*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_DMA2D	23
27*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_ETHMAC	25
28*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_ETHMACTX	26
29*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_ETHMACRX	27
30*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_ETHMACPTP	28
31*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_OTGHS		29
32*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB1_OTGHSULPI	30
33*c66ec88fSEmmanuel Vadot 
34*c66ec88fSEmmanuel Vadot #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35*c66ec88fSEmmanuel Vadot #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
36*c66ec88fSEmmanuel Vadot 
37*c66ec88fSEmmanuel Vadot 
38*c66ec88fSEmmanuel Vadot /* AHB2 */
39*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB2_DCMI	0
40*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB2_CRYP	4
41*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB2_HASH	5
42*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB2_RNG	6
43*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB2_OTGFS	7
44*c66ec88fSEmmanuel Vadot 
45*c66ec88fSEmmanuel Vadot #define STM32F4_AHB2_RESET(bit)	(STM32F4_RCC_AHB2_##bit + (0x14 * 8))
46*c66ec88fSEmmanuel Vadot #define STM32F4_AHB2_CLOCK(bit)	(STM32F4_RCC_AHB2_##bit + 0x20)
47*c66ec88fSEmmanuel Vadot 
48*c66ec88fSEmmanuel Vadot /* AHB3 */
49*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB3_FMC	0
50*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_AHB3_QSPI	1
51*c66ec88fSEmmanuel Vadot 
52*c66ec88fSEmmanuel Vadot #define STM32F4_AHB3_RESET(bit)	(STM32F4_RCC_AHB3_##bit + (0x18 * 8))
53*c66ec88fSEmmanuel Vadot #define STM32F4_AHB3_CLOCK(bit)	(STM32F4_RCC_AHB3_##bit + 0x40)
54*c66ec88fSEmmanuel Vadot 
55*c66ec88fSEmmanuel Vadot /* APB1 */
56*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_TIM2	0
57*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_TIM3	1
58*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_TIM4	2
59*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_TIM5	3
60*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_TIM6	4
61*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_TIM7	5
62*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_TIM12	6
63*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_TIM13	7
64*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_TIM14	8
65*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_WWDG	11
66*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_SPI2	14
67*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_SPI3	15
68*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_UART2	17
69*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_UART3	18
70*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_UART4	19
71*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_UART5	20
72*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_I2C1	21
73*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_I2C2	22
74*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_I2C3	23
75*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_CAN1	25
76*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_CAN2	26
77*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_PWR	28
78*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_DAC	29
79*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_UART7	30
80*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB1_UART8	31
81*c66ec88fSEmmanuel Vadot 
82*c66ec88fSEmmanuel Vadot #define STM32F4_APB1_RESET(bit)	(STM32F4_RCC_APB1_##bit + (0x20 * 8))
83*c66ec88fSEmmanuel Vadot #define STM32F4_APB1_CLOCK(bit)	(STM32F4_RCC_APB1_##bit + 0x80)
84*c66ec88fSEmmanuel Vadot 
85*c66ec88fSEmmanuel Vadot /* APB2 */
86*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_TIM1	0
87*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_TIM8	1
88*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_USART1	4
89*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_USART6	5
90*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_ADC1	8
91*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_ADC2	9
92*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_ADC3	10
93*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_SDIO	11
94*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_SPI1	12
95*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_SPI4	13
96*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_SYSCFG	14
97*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_TIM9	16
98*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_TIM10	17
99*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_TIM11	18
100*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_SPI5	20
101*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_SPI6	21
102*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_SAI1	22
103*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_LTDC	26
104*c66ec88fSEmmanuel Vadot #define STM32F4_RCC_APB2_DSI	27
105*c66ec88fSEmmanuel Vadot 
106*c66ec88fSEmmanuel Vadot #define STM32F4_APB2_RESET(bit)	(STM32F4_RCC_APB2_##bit + (0x24 * 8))
107*c66ec88fSEmmanuel Vadot #define STM32F4_APB2_CLOCK(bit)	(STM32F4_RCC_APB2_##bit + 0xA0)
108*c66ec88fSEmmanuel Vadot 
109*c66ec88fSEmmanuel Vadot #endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */
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