1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2020 MediaTek Inc. 4 * 5 * Author: Chao Hao <chao.hao@mediatek.com> 6 * Author: Yong Wu <yong.wu@mediatek.com> 7 */ 8 #ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ 9 #define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ 10 11 #include <dt-bindings/memory/mtk-memory-port.h> 12 13 /* 14 * MM IOMMU supports 16GB dma address. 15 * 16 * The address will preassign like this: 17 * 18 * modules dma-address-region larbs-ports 19 * disp 0 ~ 4G larb0/1 20 * vcodec 4G ~ 8G larb4/5/7 21 * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 22 * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 23 * CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 24 * 25 * larb3/6/8/10/12/15 is null. 26 */ 27 28 /* larb0 */ 29 #define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) 30 #define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_ID(0, 1) 31 #define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2) 32 #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 3) 33 #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 4) 34 #define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) 35 36 /* larb1 */ 37 #define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_ID(1, 0) 38 #define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_ID(1, 1) 39 #define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 2) 40 #define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_ID(1, 3) 41 #define M4U_PORT_L1_DISP_MDP_RDMA4 MTK_M4U_ID(1, 4) 42 #define M4U_PORT_L1_DISP_RDMA4 MTK_M4U_ID(1, 5) 43 #define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_ID(1, 6) 44 #define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 7) 45 46 /* larb2 */ 47 #define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) 48 #define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1) 49 #define M4U_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) 50 #define M4U_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3) 51 #define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_ID(2, 4) 52 53 /* larb3: null */ 54 55 /* larb4 */ 56 #define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_ID(4, 0) 57 #define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_ID(4, 1) 58 #define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_ID(4, 2) 59 #define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3) 60 #define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4) 61 #define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5) 62 #define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_ID(4, 6) 63 #define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_ID(4, 7) 64 #define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_ID(4, 8) 65 #define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9) 66 #define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 10) 67 68 /* larb5 */ 69 #define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_ID(5, 0) 70 #define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(5, 1) 71 #define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(5, 2) 72 #define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(5, 3) 73 #define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_ID(5, 4) 74 #define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(5, 5) 75 #define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT MTK_M4U_ID(5, 6) 76 #define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_ID(5, 7) 77 78 /* larb6: null */ 79 80 /* larb7 */ 81 #define M4U_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0) 82 #define M4U_PORT_L7_VENC_REC MTK_M4U_ID(7, 1) 83 #define M4U_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2) 84 #define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3) 85 #define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4) 86 #define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5) 87 #define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6) 88 #define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7) 89 #define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8) 90 #define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9) 91 #define M4U_PORT_L7_JPGENC_Q_RDMA MTK_M4U_ID(7, 10) 92 #define M4U_PORT_L7_JPGENC_C_TABLE MTK_M4U_ID(7, 11) 93 #define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12) 94 #define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_ID(7, 13) 95 #define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_ID(7, 14) 96 97 /* larb8: null */ 98 99 /* larb9 */ 100 #define M4U_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0) 101 #define M4U_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1) 102 #define M4U_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2) 103 #define M4U_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3) 104 #define M4U_PORT_L9_IMG_ICE_D1 MTK_M4U_ID(9, 4) 105 #define M4U_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5) 106 #define M4U_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6) 107 #define M4U_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7) 108 #define M4U_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8) 109 #define M4U_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9) 110 #define M4U_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10) 111 #define M4U_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11) 112 #define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12) 113 #define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13) 114 #define M4U_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14) 115 116 /* larb10: null */ 117 118 /* larb11 */ 119 #define M4U_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0) 120 #define M4U_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1) 121 #define M4U_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2) 122 #define M4U_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3) 123 #define M4U_PORT_L11_IMG_ICE_D1 MTK_M4U_ID(11, 4) 124 #define M4U_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5) 125 #define M4U_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6) 126 #define M4U_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7) 127 #define M4U_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8) 128 #define M4U_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9) 129 #define M4U_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10) 130 #define M4U_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11) 131 #define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12) 132 #define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13) 133 #define M4U_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14) 134 #define M4U_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15) 135 #define M4U_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) 136 #define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17) 137 #define M4U_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18) 138 #define M4U_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19) 139 #define M4U_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20) 140 #define M4U_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21) 141 #define M4U_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22) 142 #define M4U_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23) 143 #define M4U_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24) 144 #define M4U_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25) 145 146 /* larb12: null */ 147 148 /* larb13 */ 149 #define M4U_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0) 150 #define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_ID(13, 1) 151 #define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_ID(13, 2) 152 #define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_ID(13, 3) 153 #define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_ID(13, 4) 154 #define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_ID(13, 5) 155 #define M4U_PORT_L13_CAM_CAMSV4 MTK_M4U_ID(13, 6) 156 #define M4U_PORT_L13_CAM_CAMSV5 MTK_M4U_ID(13, 7) 157 #define M4U_PORT_L13_CAM_CAMSV6 MTK_M4U_ID(13, 8) 158 #define M4U_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9) 159 #define M4U_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10) 160 #define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11) 161 162 /* larb14 */ 163 #define M4U_PORT_L14_CAM_RESERVE1 MTK_M4U_ID(14, 0) 164 #define M4U_PORT_L14_CAM_RESERVE2 MTK_M4U_ID(14, 1) 165 #define M4U_PORT_L14_CAM_RESERVE3 MTK_M4U_ID(14, 2) 166 #define M4U_PORT_L14_CAM_CAMSV0 MTK_M4U_ID(14, 3) 167 #define M4U_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4) 168 #define M4U_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5) 169 170 /* larb15: null */ 171 172 /* larb16 */ 173 #define M4U_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0) 174 #define M4U_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1) 175 #define M4U_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2) 176 #define M4U_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3) 177 #define M4U_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4) 178 #define M4U_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5) 179 #define M4U_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6) 180 #define M4U_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7) 181 #define M4U_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8) 182 #define M4U_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9) 183 #define M4U_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10) 184 #define M4U_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11) 185 #define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12) 186 #define M4U_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13) 187 #define M4U_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14) 188 #define M4U_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15) 189 #define M4U_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16) 190 191 /* larb17 */ 192 #define M4U_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0) 193 #define M4U_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1) 194 #define M4U_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2) 195 #define M4U_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3) 196 #define M4U_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4) 197 #define M4U_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5) 198 #define M4U_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6) 199 #define M4U_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7) 200 #define M4U_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8) 201 #define M4U_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9) 202 #define M4U_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10) 203 #define M4U_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11) 204 #define M4U_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12) 205 #define M4U_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13) 206 #define M4U_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14) 207 #define M4U_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15) 208 #define M4U_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16) 209 210 /* larb18 */ 211 #define M4U_PORT_L18_CAM_IMGO_R1_C MTK_M4U_ID(18, 0) 212 #define M4U_PORT_L18_CAM_RRZO_R1_C MTK_M4U_ID(18, 1) 213 #define M4U_PORT_L18_CAM_CQI_R1_C MTK_M4U_ID(18, 2) 214 #define M4U_PORT_L18_CAM_BPCI_R1_C MTK_M4U_ID(18, 3) 215 #define M4U_PORT_L18_CAM_YUVO_R1_C MTK_M4U_ID(18, 4) 216 #define M4U_PORT_L18_CAM_UFDI_R2_C MTK_M4U_ID(18, 5) 217 #define M4U_PORT_L18_CAM_RAWI_R2_C MTK_M4U_ID(18, 6) 218 #define M4U_PORT_L18_CAM_RAWI_R3_C MTK_M4U_ID(18, 7) 219 #define M4U_PORT_L18_CAM_AAO_R1_C MTK_M4U_ID(18, 8) 220 #define M4U_PORT_L18_CAM_AFO_R1_C MTK_M4U_ID(18, 9) 221 #define M4U_PORT_L18_CAM_FLKO_R1_C MTK_M4U_ID(18, 10) 222 #define M4U_PORT_L18_CAM_LCESO_R1_C MTK_M4U_ID(18, 11) 223 #define M4U_PORT_L18_CAM_CRZO_R1_C MTK_M4U_ID(18, 12) 224 #define M4U_PORT_L18_CAM_LTMSO_R1_C MTK_M4U_ID(18, 13) 225 #define M4U_PORT_L18_CAM_RSSO_R1_C MTK_M4U_ID(18, 14) 226 #define M4U_PORT_L18_CAM_AAHO_R1_C MTK_M4U_ID(18, 15) 227 #define M4U_PORT_L18_CAM_LSCI_R1_C MTK_M4U_ID(18, 16) 228 229 /* larb19 */ 230 #define M4U_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0) 231 #define M4U_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1) 232 #define M4U_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2) 233 #define M4U_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3) 234 235 /* larb20 */ 236 #define M4U_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0) 237 #define M4U_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1) 238 #define M4U_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2) 239 #define M4U_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3) 240 #define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) 241 #define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) 242 243 #endif 244