1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * This header provides clock numbers for the ingenic,x1000-cgu DT binding. 4 * 5 * They are roughly ordered as: 6 * - external clocks 7 * - PLLs 8 * - muxes/dividers in the order they appear in the x1000 programmers manual 9 * - gates in order of their bit in the CLKGR* registers 10 */ 11 12 #ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ 13 #define __DT_BINDINGS_CLOCK_X1000_CGU_H__ 14 15 #define X1000_CLK_EXCLK 0 16 #define X1000_CLK_RTCLK 1 17 #define X1000_CLK_APLL 2 18 #define X1000_CLK_MPLL 3 19 #define X1000_CLK_OTGPHY 4 20 #define X1000_CLK_SCLKA 5 21 #define X1000_CLK_CPUMUX 6 22 #define X1000_CLK_CPU 7 23 #define X1000_CLK_L2CACHE 8 24 #define X1000_CLK_AHB0 9 25 #define X1000_CLK_AHB2PMUX 10 26 #define X1000_CLK_AHB2 11 27 #define X1000_CLK_PCLK 12 28 #define X1000_CLK_DDR 13 29 #define X1000_CLK_MAC 14 30 #define X1000_CLK_LCD 15 31 #define X1000_CLK_MSCMUX 16 32 #define X1000_CLK_MSC0 17 33 #define X1000_CLK_MSC1 18 34 #define X1000_CLK_OTG 19 35 #define X1000_CLK_SSIPLL 20 36 #define X1000_CLK_SSIPLL_DIV2 21 37 #define X1000_CLK_SSIMUX 22 38 #define X1000_CLK_EMC 23 39 #define X1000_CLK_EFUSE 24 40 #define X1000_CLK_SFC 25 41 #define X1000_CLK_I2C0 26 42 #define X1000_CLK_I2C1 27 43 #define X1000_CLK_I2C2 28 44 #define X1000_CLK_UART0 29 45 #define X1000_CLK_UART1 30 46 #define X1000_CLK_UART2 31 47 #define X1000_CLK_TCU 32 48 #define X1000_CLK_SSI 33 49 #define X1000_CLK_OST 34 50 #define X1000_CLK_PDMA 35 51 #define X1000_CLK_EXCLK_DIV512 36 52 #define X1000_CLK_RTC 37 53 54 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ 55