1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * This header provides constants for binding nvidia,tegra20-car. 4 * 5 * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 6 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 7 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 8 * this case, those clocks are assigned IDs above 95 in order to highlight 9 * this issue. Implementations that interpret these clock IDs as bit values 10 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 11 * explicitly handle these special cases. 12 * 13 * The balance of the clocks controlled by the CAR are assigned IDs of 96 and 14 * above. 15 */ 16 17 #ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H 18 #define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H 19 20 #define TEGRA20_CLK_CPU 0 21 /* 1 */ 22 /* 2 */ 23 #define TEGRA20_CLK_AC97 3 24 #define TEGRA20_CLK_RTC 4 25 #define TEGRA20_CLK_TIMER 5 26 #define TEGRA20_CLK_UARTA 6 27 /* 7 (register bit affects uart2 and vfir) */ 28 #define TEGRA20_CLK_GPIO 8 29 #define TEGRA20_CLK_SDMMC2 9 30 /* 10 (register bit affects spdif_in and spdif_out) */ 31 #define TEGRA20_CLK_I2S1 11 32 #define TEGRA20_CLK_I2C1 12 33 #define TEGRA20_CLK_NDFLASH 13 34 #define TEGRA20_CLK_SDMMC1 14 35 #define TEGRA20_CLK_SDMMC4 15 36 #define TEGRA20_CLK_TWC 16 37 #define TEGRA20_CLK_PWM 17 38 #define TEGRA20_CLK_I2S2 18 39 #define TEGRA20_CLK_EPP 19 40 /* 20 (register bit affects vi and vi_sensor) */ 41 #define TEGRA20_CLK_GR2D 21 42 #define TEGRA20_CLK_USBD 22 43 #define TEGRA20_CLK_ISP 23 44 #define TEGRA20_CLK_GR3D 24 45 #define TEGRA20_CLK_IDE 25 46 #define TEGRA20_CLK_DISP2 26 47 #define TEGRA20_CLK_DISP1 27 48 #define TEGRA20_CLK_HOST1X 28 49 #define TEGRA20_CLK_VCP 29 50 /* 30 */ 51 #define TEGRA20_CLK_CACHE2 31 52 53 #define TEGRA20_CLK_MC 32 54 #define TEGRA20_CLK_AHBDMA 33 55 #define TEGRA20_CLK_APBDMA 34 56 /* 35 */ 57 #define TEGRA20_CLK_KBC 36 58 #define TEGRA20_CLK_STAT_MON 37 59 #define TEGRA20_CLK_PMC 38 60 #define TEGRA20_CLK_FUSE 39 61 #define TEGRA20_CLK_KFUSE 40 62 #define TEGRA20_CLK_SBC1 41 63 #define TEGRA20_CLK_NOR 42 64 #define TEGRA20_CLK_SPI 43 65 #define TEGRA20_CLK_SBC2 44 66 #define TEGRA20_CLK_XIO 45 67 #define TEGRA20_CLK_SBC3 46 68 #define TEGRA20_CLK_DVC 47 69 #define TEGRA20_CLK_DSI 48 70 /* 49 (register bit affects tvo and cve) */ 71 #define TEGRA20_CLK_MIPI 50 72 #define TEGRA20_CLK_HDMI 51 73 #define TEGRA20_CLK_CSI 52 74 #define TEGRA20_CLK_TVDAC 53 75 #define TEGRA20_CLK_I2C2 54 76 #define TEGRA20_CLK_UARTC 55 77 /* 56 */ 78 #define TEGRA20_CLK_EMC 57 79 #define TEGRA20_CLK_USB2 58 80 #define TEGRA20_CLK_USB3 59 81 #define TEGRA20_CLK_MPE 60 82 #define TEGRA20_CLK_VDE 61 83 #define TEGRA20_CLK_BSEA 62 84 #define TEGRA20_CLK_BSEV 63 85 86 #define TEGRA20_CLK_SPEEDO 64 87 #define TEGRA20_CLK_UARTD 65 88 #define TEGRA20_CLK_UARTE 66 89 #define TEGRA20_CLK_I2C3 67 90 #define TEGRA20_CLK_SBC4 68 91 #define TEGRA20_CLK_SDMMC3 69 92 #define TEGRA20_CLK_PEX 70 93 #define TEGRA20_CLK_OWR 71 94 #define TEGRA20_CLK_AFI 72 95 #define TEGRA20_CLK_CSITE 73 96 /* 74 */ 97 #define TEGRA20_CLK_AVPUCQ 75 98 #define TEGRA20_CLK_LA 76 99 /* 77 */ 100 /* 78 */ 101 /* 79 */ 102 /* 80 */ 103 /* 81 */ 104 /* 82 */ 105 /* 83 */ 106 #define TEGRA20_CLK_IRAMA 84 107 #define TEGRA20_CLK_IRAMB 85 108 #define TEGRA20_CLK_IRAMC 86 109 #define TEGRA20_CLK_IRAMD 87 110 #define TEGRA20_CLK_CRAM2 88 111 #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ 112 #define TEGRA20_CLK_CLK_D 90 113 /* 91 */ 114 #define TEGRA20_CLK_CSUS 92 115 #define TEGRA20_CLK_CDEV2 93 116 #define TEGRA20_CLK_CDEV1 94 117 /* 95 */ 118 119 #define TEGRA20_CLK_UARTB 96 120 #define TEGRA20_CLK_VFIR 97 121 #define TEGRA20_CLK_SPDIF_IN 98 122 #define TEGRA20_CLK_SPDIF_OUT 99 123 #define TEGRA20_CLK_VI 100 124 #define TEGRA20_CLK_VI_SENSOR 101 125 #define TEGRA20_CLK_TVO 102 126 #define TEGRA20_CLK_CVE 103 127 #define TEGRA20_CLK_OSC 104 128 #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ 129 #define TEGRA20_CLK_CLK_M 106 130 #define TEGRA20_CLK_SCLK 107 131 #define TEGRA20_CLK_CCLK 108 132 #define TEGRA20_CLK_HCLK 109 133 #define TEGRA20_CLK_PCLK 110 134 /* 111 */ 135 #define TEGRA20_CLK_PLL_A 112 136 #define TEGRA20_CLK_PLL_A_OUT0 113 137 #define TEGRA20_CLK_PLL_C 114 138 #define TEGRA20_CLK_PLL_C_OUT1 115 139 #define TEGRA20_CLK_PLL_D 116 140 #define TEGRA20_CLK_PLL_D_OUT0 117 141 #define TEGRA20_CLK_PLL_E 118 142 #define TEGRA20_CLK_PLL_M 119 143 #define TEGRA20_CLK_PLL_M_OUT1 120 144 #define TEGRA20_CLK_PLL_P 121 145 #define TEGRA20_CLK_PLL_P_OUT1 122 146 #define TEGRA20_CLK_PLL_P_OUT2 123 147 #define TEGRA20_CLK_PLL_P_OUT3 124 148 #define TEGRA20_CLK_PLL_P_OUT4 125 149 #define TEGRA20_CLK_PLL_S 126 150 #define TEGRA20_CLK_PLL_U 127 151 152 #define TEGRA20_CLK_PLL_X 128 153 #define TEGRA20_CLK_COP 129 /* a/k/a avp */ 154 #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ 155 #define TEGRA20_CLK_PLL_REF 131 156 #define TEGRA20_CLK_TWD 132 157 #define TEGRA20_CLK_CLK_MAX 133 158 159 #endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ 160