xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/stm32fx-clock.h (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */
2*c66ec88fSEmmanuel Vadot /*
3*c66ec88fSEmmanuel Vadot  * stm32fx-clock.h
4*c66ec88fSEmmanuel Vadot  *
5*c66ec88fSEmmanuel Vadot  * Copyright (C) 2016 STMicroelectronics
6*c66ec88fSEmmanuel Vadot  * Author: Gabriel Fernandez for STMicroelectronics.
7*c66ec88fSEmmanuel Vadot  */
8*c66ec88fSEmmanuel Vadot 
9*c66ec88fSEmmanuel Vadot /*
10*c66ec88fSEmmanuel Vadot  * List of clocks wich are not derived from system clock (SYSCLOCK)
11*c66ec88fSEmmanuel Vadot  *
12*c66ec88fSEmmanuel Vadot  * The index of these clocks is the secondary index of DT bindings
13*c66ec88fSEmmanuel Vadot  * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
14*c66ec88fSEmmanuel Vadot  *
15*c66ec88fSEmmanuel Vadot  * e.g:
16*c66ec88fSEmmanuel Vadot 	<assigned-clocks = <&rcc 1 CLK_LSE>;
17*c66ec88fSEmmanuel Vadot */
18*c66ec88fSEmmanuel Vadot 
19*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_STMFX_H
20*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLK_STMFX_H
21*c66ec88fSEmmanuel Vadot 
22*c66ec88fSEmmanuel Vadot #define SYSTICK			0
23*c66ec88fSEmmanuel Vadot #define FCLK			1
24*c66ec88fSEmmanuel Vadot #define CLK_LSI			2
25*c66ec88fSEmmanuel Vadot #define CLK_LSE			3
26*c66ec88fSEmmanuel Vadot #define CLK_HSE_RTC		4
27*c66ec88fSEmmanuel Vadot #define CLK_RTC			5
28*c66ec88fSEmmanuel Vadot #define PLL_VCO_I2S		6
29*c66ec88fSEmmanuel Vadot #define PLL_VCO_SAI		7
30*c66ec88fSEmmanuel Vadot #define CLK_LCD			8
31*c66ec88fSEmmanuel Vadot #define CLK_I2S			9
32*c66ec88fSEmmanuel Vadot #define CLK_SAI1		10
33*c66ec88fSEmmanuel Vadot #define CLK_SAI2		11
34*c66ec88fSEmmanuel Vadot #define CLK_I2SQ_PDIV		12
35*c66ec88fSEmmanuel Vadot #define CLK_SAIQ_PDIV		13
36*c66ec88fSEmmanuel Vadot #define CLK_HSI			14
37*c66ec88fSEmmanuel Vadot #define CLK_SYSCLK		15
38*c66ec88fSEmmanuel Vadot #define CLK_F469_DSI		16
39*c66ec88fSEmmanuel Vadot 
40*c66ec88fSEmmanuel Vadot #define END_PRIMARY_CLK		17
41*c66ec88fSEmmanuel Vadot 
42*c66ec88fSEmmanuel Vadot #define CLK_HDMI_CEC		16
43*c66ec88fSEmmanuel Vadot #define CLK_SPDIF		17
44*c66ec88fSEmmanuel Vadot #define CLK_USART1		18
45*c66ec88fSEmmanuel Vadot #define CLK_USART2		19
46*c66ec88fSEmmanuel Vadot #define CLK_USART3		20
47*c66ec88fSEmmanuel Vadot #define CLK_UART4		21
48*c66ec88fSEmmanuel Vadot #define CLK_UART5		22
49*c66ec88fSEmmanuel Vadot #define CLK_USART6		23
50*c66ec88fSEmmanuel Vadot #define CLK_UART7		24
51*c66ec88fSEmmanuel Vadot #define CLK_UART8		25
52*c66ec88fSEmmanuel Vadot #define CLK_I2C1		26
53*c66ec88fSEmmanuel Vadot #define CLK_I2C2		27
54*c66ec88fSEmmanuel Vadot #define CLK_I2C3		28
55*c66ec88fSEmmanuel Vadot #define CLK_I2C4		29
56*c66ec88fSEmmanuel Vadot #define CLK_LPTIMER		30
57*c66ec88fSEmmanuel Vadot #define CLK_PLL_SRC		31
58*c66ec88fSEmmanuel Vadot #define CLK_DFSDM1		32
59*c66ec88fSEmmanuel Vadot #define CLK_ADFSDM1		33
60*c66ec88fSEmmanuel Vadot #define CLK_F769_DSI		34
61*c66ec88fSEmmanuel Vadot #define END_PRIMARY_CLK_F7	35
62*c66ec88fSEmmanuel Vadot 
63*c66ec88fSEmmanuel Vadot #endif
64