1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright (C) 2019 SiFive, Inc. 4 * Wesley Terpstra 5 * Paul Walmsley 6 * Zong Li 7 */ 8 9 #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H 10 #define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H 11 12 /* Clock indexes for use by Device Tree data and the PRCI driver */ 13 14 #define PRCI_CLK_COREPLL 0 15 #define PRCI_CLK_DDRPLL 1 16 #define PRCI_CLK_GEMGXLPLL 2 17 #define PRCI_CLK_DVFSCOREPLL 3 18 #define PRCI_CLK_HFPCLKPLL 4 19 #define PRCI_CLK_CLTXPLL 5 20 #define PRCI_CLK_TLCLK 6 21 #define PRCI_CLK_PCLK 7 22 #define PRCI_CLK_PCIE_AUX 8 23 24 #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ 25