1*5def4c47SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*5def4c47SEmmanuel Vadot /* 3*5def4c47SEmmanuel Vadot * Copyright (C) 2019 SiFive, Inc. 4*5def4c47SEmmanuel Vadot * Wesley Terpstra 5*5def4c47SEmmanuel Vadot * Paul Walmsley 6*5def4c47SEmmanuel Vadot * Zong Li 7*5def4c47SEmmanuel Vadot */ 8*5def4c47SEmmanuel Vadot 9*5def4c47SEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H 10*5def4c47SEmmanuel Vadot #define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H 11*5def4c47SEmmanuel Vadot 12*5def4c47SEmmanuel Vadot /* Clock indexes for use by Device Tree data and the PRCI driver */ 13*5def4c47SEmmanuel Vadot 14*5def4c47SEmmanuel Vadot #define PRCI_CLK_COREPLL 0 15*5def4c47SEmmanuel Vadot #define PRCI_CLK_DDRPLL 1 16*5def4c47SEmmanuel Vadot #define PRCI_CLK_GEMGXLPLL 2 17*5def4c47SEmmanuel Vadot #define PRCI_CLK_DVFSCOREPLL 3 18*5def4c47SEmmanuel Vadot #define PRCI_CLK_HFPCLKPLL 4 19*5def4c47SEmmanuel Vadot #define PRCI_CLK_CLTXPLL 5 20*5def4c47SEmmanuel Vadot #define PRCI_CLK_TLCLK 6 21*5def4c47SEmmanuel Vadot #define PRCI_CLK_PCLK 7 22*5def4c47SEmmanuel Vadot 23*5def4c47SEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ 24