1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2018-2019 SiFive, Inc. 4*c66ec88fSEmmanuel Vadot * Wesley Terpstra 5*c66ec88fSEmmanuel Vadot * Paul Walmsley 6*c66ec88fSEmmanuel Vadot */ 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H 9*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel Vadot /* Clock indexes for use by Device Tree data and the PRCI driver */ 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel Vadot #define PRCI_CLK_COREPLL 0 14*c66ec88fSEmmanuel Vadot #define PRCI_CLK_DDRPLL 1 15*c66ec88fSEmmanuel Vadot #define PRCI_CLK_GEMGXLPLL 2 16*c66ec88fSEmmanuel Vadot #define PRCI_CLK_TLCLK 3 17*c66ec88fSEmmanuel Vadot 18*c66ec88fSEmmanuel Vadot #endif 19