xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/sh73a0-clock.h (revision fe75646a0234a261c0013bf1840fdac4acaf0cec)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright 2014 Ulrich Hecht
4  */
5 
6 #ifndef __DT_BINDINGS_CLOCK_SH73A0_H__
7 #define __DT_BINDINGS_CLOCK_SH73A0_H__
8 
9 /* CPG */
10 #define SH73A0_CLK_MAIN		0
11 #define SH73A0_CLK_PLL0		1
12 #define SH73A0_CLK_PLL1		2
13 #define SH73A0_CLK_PLL2		3
14 #define SH73A0_CLK_PLL3		4
15 #define SH73A0_CLK_DSI0PHY	5
16 #define SH73A0_CLK_DSI1PHY	6
17 #define SH73A0_CLK_ZG		7
18 #define SH73A0_CLK_M3		8
19 #define SH73A0_CLK_B		9
20 #define SH73A0_CLK_M1		10
21 #define SH73A0_CLK_M2		11
22 #define SH73A0_CLK_Z		12
23 #define SH73A0_CLK_ZX		13
24 #define SH73A0_CLK_HP		14
25 
26 /* MSTP0 */
27 #define SH73A0_CLK_IIC2		1
28 #define SH73A0_CLK_MSIOF0	0
29 
30 /* MSTP1 */
31 #define SH73A0_CLK_CEU1		29
32 #define SH73A0_CLK_CSI2_RX1	28
33 #define SH73A0_CLK_CEU0		27
34 #define SH73A0_CLK_CSI2_RX0	26
35 #define SH73A0_CLK_TMU0		25
36 #define SH73A0_CLK_DSITX0	18
37 #define SH73A0_CLK_IIC0		16
38 #define SH73A0_CLK_SGX		12
39 #define SH73A0_CLK_LCDC0	0
40 
41 /* MSTP2 */
42 #define SH73A0_CLK_SCIFA7	19
43 #define SH73A0_CLK_SY_DMAC	18
44 #define SH73A0_CLK_MP_DMAC	17
45 #define SH73A0_CLK_MSIOF3	15
46 #define SH73A0_CLK_MSIOF1	8
47 #define SH73A0_CLK_SCIFA5	7
48 #define SH73A0_CLK_SCIFB	6
49 #define SH73A0_CLK_MSIOF2	5
50 #define SH73A0_CLK_SCIFA0	4
51 #define SH73A0_CLK_SCIFA1	3
52 #define SH73A0_CLK_SCIFA2	2
53 #define SH73A0_CLK_SCIFA3	1
54 #define SH73A0_CLK_SCIFA4	0
55 
56 /* MSTP3 */
57 #define SH73A0_CLK_SCIFA6	31
58 #define SH73A0_CLK_CMT1		29
59 #define SH73A0_CLK_FSI		28
60 #define SH73A0_CLK_IRDA		25
61 #define SH73A0_CLK_IIC1		23
62 #define SH73A0_CLK_USB		22
63 #define SH73A0_CLK_FLCTL	15
64 #define SH73A0_CLK_SDHI0	14
65 #define SH73A0_CLK_SDHI1	13
66 #define SH73A0_CLK_MMCIF0	12
67 #define SH73A0_CLK_SDHI2	11
68 #define SH73A0_CLK_TPU0		4
69 #define SH73A0_CLK_TPU1		3
70 #define SH73A0_CLK_TPU2		2
71 #define SH73A0_CLK_TPU3		1
72 #define SH73A0_CLK_TPU4		0
73 
74 /* MSTP4 */
75 #define SH73A0_CLK_IIC3		11
76 #define SH73A0_CLK_IIC4		10
77 #define SH73A0_CLK_KEYSC	3
78 
79 /* MSTP5 */
80 #define SH73A0_CLK_INTCA0	8
81 
82 #endif
83