1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 4 * Author: Xing Zheng <zhengxing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H 9 10 /* core clocks */ 11 #define PLL_APLL 1 12 #define PLL_DPLL 2 13 #define PLL_GPLL 3 14 #define ARMCLK 4 15 16 /* sclk gates (special clocks) */ 17 #define SCLK_GPU 64 18 #define SCLK_SPI 65 19 #define SCLK_SDMMC 68 20 #define SCLK_SDIO 69 21 #define SCLK_EMMC 71 22 #define SCLK_NANDC 76 23 #define SCLK_UART0 77 24 #define SCLK_UART1 78 25 #define SCLK_UART2 79 26 #define SCLK_I2S 82 27 #define SCLK_SPDIF 83 28 #define SCLK_TIMER0 85 29 #define SCLK_TIMER1 86 30 #define SCLK_TIMER2 87 31 #define SCLK_TIMER3 88 32 #define SCLK_OTGPHY0 93 33 #define SCLK_LCDC 100 34 #define SCLK_HDMI 109 35 #define SCLK_HEVC 111 36 #define SCLK_I2S_OUT 113 37 #define SCLK_SDMMC_DRV 114 38 #define SCLK_SDIO_DRV 115 39 #define SCLK_EMMC_DRV 117 40 #define SCLK_SDMMC_SAMPLE 118 41 #define SCLK_SDIO_SAMPLE 119 42 #define SCLK_EMMC_SAMPLE 121 43 #define SCLK_PVTM_CORE 123 44 #define SCLK_PVTM_GPU 124 45 #define SCLK_PVTM_VIDEO 125 46 #define SCLK_MAC 151 47 #define SCLK_MACREF 152 48 #define SCLK_MACPLL 153 49 #define SCLK_SFC 160 50 51 /* aclk gates */ 52 #define ACLK_DMAC2 194 53 #define ACLK_LCDC 197 54 #define ACLK_VIO 203 55 #define ACLK_VCODEC 208 56 #define ACLK_CPU 209 57 #define ACLK_PERI 210 58 59 /* pclk gates */ 60 #define PCLK_GPIO0 320 61 #define PCLK_GPIO1 321 62 #define PCLK_GPIO2 322 63 #define PCLK_GRF 329 64 #define PCLK_I2C0 332 65 #define PCLK_I2C1 333 66 #define PCLK_I2C2 334 67 #define PCLK_SPI 338 68 #define PCLK_UART0 341 69 #define PCLK_UART1 342 70 #define PCLK_UART2 343 71 #define PCLK_PWM 350 72 #define PCLK_TIMER 353 73 #define PCLK_HDMI 360 74 #define PCLK_CPU 362 75 #define PCLK_PERI 363 76 #define PCLK_DDRUPCTL 364 77 #define PCLK_WDT 368 78 #define PCLK_ACODEC 369 79 80 /* hclk gates */ 81 #define HCLK_OTG0 449 82 #define HCLK_OTG1 450 83 #define HCLK_NANDC 453 84 #define HCLK_SFC 454 85 #define HCLK_SDMMC 456 86 #define HCLK_SDIO 457 87 #define HCLK_EMMC 459 88 #define HCLK_MAC 460 89 #define HCLK_I2S 462 90 #define HCLK_LCDC 465 91 #define HCLK_ROM 467 92 #define HCLK_VIO_BUS 472 93 #define HCLK_VCODEC 476 94 #define HCLK_CPU 477 95 #define HCLK_PERI 478 96 97 #define CLK_NR_CLKS (HCLK_PERI + 1) 98 99 /* soft-reset indices */ 100 #define SRST_CORE0 0 101 #define SRST_CORE1 1 102 #define SRST_CORE0_DBG 4 103 #define SRST_CORE1_DBG 5 104 #define SRST_CORE0_POR 8 105 #define SRST_CORE1_POR 9 106 #define SRST_L2C 12 107 #define SRST_TOPDBG 13 108 #define SRST_STRC_SYS_A 14 109 #define SRST_PD_CORE_NIU 15 110 111 #define SRST_TIMER2 16 112 #define SRST_CPUSYS_H 17 113 #define SRST_AHB2APB_H 19 114 #define SRST_TIMER3 20 115 #define SRST_INTMEM 21 116 #define SRST_ROM 22 117 #define SRST_PERI_NIU 23 118 #define SRST_I2S 24 119 #define SRST_DDR_PLL 25 120 #define SRST_GPU_DLL 26 121 #define SRST_TIMER0 27 122 #define SRST_TIMER1 28 123 #define SRST_CORE_DLL 29 124 #define SRST_EFUSE_P 30 125 #define SRST_ACODEC_P 31 126 127 #define SRST_GPIO0 32 128 #define SRST_GPIO1 33 129 #define SRST_GPIO2 34 130 #define SRST_UART0 39 131 #define SRST_UART1 40 132 #define SRST_UART2 41 133 #define SRST_I2C0 43 134 #define SRST_I2C1 44 135 #define SRST_I2C2 45 136 #define SRST_SFC 47 137 138 #define SRST_PWM0 48 139 #define SRST_DAP 51 140 #define SRST_DAP_SYS 52 141 #define SRST_GRF 55 142 #define SRST_PERIPHSYS_A 57 143 #define SRST_PERIPHSYS_H 58 144 #define SRST_PERIPHSYS_P 59 145 #define SRST_CPU_PERI 61 146 #define SRST_EMEM_PERI 62 147 #define SRST_USB_PERI 63 148 149 #define SRST_DMA2 64 150 #define SRST_MAC 66 151 #define SRST_NANDC 68 152 #define SRST_USBOTG0 69 153 #define SRST_OTGC0 71 154 #define SRST_USBOTG1 72 155 #define SRST_OTGC1 74 156 #define SRST_DDRMSCH 79 157 158 #define SRST_MMC0 81 159 #define SRST_SDIO 82 160 #define SRST_EMMC 83 161 #define SRST_SPI0 84 162 #define SRST_WDT 86 163 #define SRST_DDRPHY 88 164 #define SRST_DDRPHY_P 89 165 #define SRST_DDRCTRL 90 166 #define SRST_DDRCTRL_P 91 167 168 #define SRST_HDMI_P 96 169 #define SRST_VIO_BUS_H 99 170 #define SRST_UTMI0 103 171 #define SRST_UTMI1 104 172 #define SRST_USBPOR 105 173 174 #define SRST_VCODEC_A 112 175 #define SRST_VCODEC_H 113 176 #define SRST_VIO1_A 114 177 #define SRST_HEVC 115 178 #define SRST_VCODEC_NIU_A 116 179 #define SRST_LCDC1_A 117 180 #define SRST_LCDC1_H 118 181 #define SRST_LCDC1_D 119 182 #define SRST_GPU 120 183 #define SRST_GPU_NIU_A 122 184 185 #define SRST_DBG_P 131 186 187 #endif 188