1ae5de77eSEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2ae5de77eSEmmanuel Vadot * 3ae5de77eSEmmanuel Vadot * Copyright (C) 2025 Renesas Electronics Corp. 4ae5de77eSEmmanuel Vadot */ 5ae5de77eSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 6ae5de77eSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 7ae5de77eSEmmanuel Vadot 8ae5de77eSEmmanuel Vadot #include <dt-bindings/clock/renesas-cpg-mssr.h> 9ae5de77eSEmmanuel Vadot 10ae5de77eSEmmanuel Vadot /* Core Clock list */ 11ae5de77eSEmmanuel Vadot #define R9A09G056_SYS_0_PCLK 0 12ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_CORE_CLK0 1 13ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_CORE_CLK1 2 14ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_CORE_CLK2 3 15ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_CORE_CLK3 4 16ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_PERIPHCLK 5 17ae5de77eSEmmanuel Vadot #define R9A09G056_CM33_CLK0 6 18ae5de77eSEmmanuel Vadot #define R9A09G056_CST_0_SWCLKTCK 7 19ae5de77eSEmmanuel Vadot #define R9A09G056_IOTOP_0_SHCLK 8 20ae5de77eSEmmanuel Vadot #define R9A09G056_USB2_0_CLK_CORE0 9 21ae5de77eSEmmanuel Vadot #define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 22ae5de77eSEmmanuel Vadot #define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 23*833e5d42SEmmanuel Vadot #define R9A09G056_SPI_CLK_SPI 12 24ae5de77eSEmmanuel Vadot 25ae5de77eSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ 26