12846c905SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 22846c905SEmmanuel Vadot * 32846c905SEmmanuel Vadot * Copyright (C) 2024 Renesas Electronics Corp. 42846c905SEmmanuel Vadot */ 52846c905SEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ 62846c905SEmmanuel Vadot #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ 72846c905SEmmanuel Vadot 82846c905SEmmanuel Vadot #include <dt-bindings/clock/renesas-cpg-mssr.h> 92846c905SEmmanuel Vadot 102846c905SEmmanuel Vadot /* Core Clock list */ 112846c905SEmmanuel Vadot #define R9A09G047_SYS_0_PCLK 0 122846c905SEmmanuel Vadot #define R9A09G047_CA55_0_CORECLK0 1 132846c905SEmmanuel Vadot #define R9A09G047_CA55_0_CORECLK1 2 142846c905SEmmanuel Vadot #define R9A09G047_CA55_0_CORECLK2 3 152846c905SEmmanuel Vadot #define R9A09G047_CA55_0_CORECLK3 4 162846c905SEmmanuel Vadot #define R9A09G047_CA55_0_PERIPHCLK 5 172846c905SEmmanuel Vadot #define R9A09G047_CM33_CLK0 6 182846c905SEmmanuel Vadot #define R9A09G047_CST_0_SWCLKTCK 7 192846c905SEmmanuel Vadot #define R9A09G047_IOTOP_0_SHCLK 8 20*ae5de77eSEmmanuel Vadot #define R9A09G047_SPI_CLK_SPI 9 21*ae5de77eSEmmanuel Vadot #define R9A09G047_GBETH_0_CLK_PTP_REF_I 10 22*ae5de77eSEmmanuel Vadot #define R9A09G047_GBETH_1_CLK_PTP_REF_I 11 232846c905SEmmanuel Vadot 242846c905SEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ 25