1*833e5d42SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*833e5d42SEmmanuel Vadot * 3*833e5d42SEmmanuel Vadot * Copyright (C) 2025 Renesas Electronics Corp. 4*833e5d42SEmmanuel Vadot */ 5*833e5d42SEmmanuel Vadot 6*833e5d42SEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 7*833e5d42SEmmanuel Vadot #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 8*833e5d42SEmmanuel Vadot 9*833e5d42SEmmanuel Vadot #include <dt-bindings/clock/renesas-cpg-mssr.h> 10*833e5d42SEmmanuel Vadot 11*833e5d42SEmmanuel Vadot /* R9A09G077 CPG Core Clocks */ 12*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_CA55C0 0 13*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_CA55C1 1 14*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_CA55C2 2 15*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_CA55C3 3 16*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_CA55S 4 17*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_CR52_CPU0 5 18*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_CR52_CPU1 6 19*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_CKIO 7 20*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_PCLKAH 8 21*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_PCLKAM 9 22*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_PCLKAL 10 23*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_PCLKGPTL 11 24*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_PCLKH 12 25*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_PCLKM 13 26*833e5d42SEmmanuel Vadot #define R9A09G077_CLK_PCLKL 14 27*833e5d42SEmmanuel Vadot #define R9A09G077_SDHI_CLKHS 15 28*833e5d42SEmmanuel Vadot 29*833e5d42SEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ 30