1*ae5de77eSEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*ae5de77eSEmmanuel Vadot * 3*ae5de77eSEmmanuel Vadot * Copyright (C) 2025 Renesas Electronics Corp. 4*ae5de77eSEmmanuel Vadot */ 5*ae5de77eSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 6*ae5de77eSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ 7*ae5de77eSEmmanuel Vadot 8*ae5de77eSEmmanuel Vadot #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*ae5de77eSEmmanuel Vadot 10*ae5de77eSEmmanuel Vadot /* Core Clock list */ 11*ae5de77eSEmmanuel Vadot #define R9A09G056_SYS_0_PCLK 0 12*ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_CORE_CLK0 1 13*ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_CORE_CLK1 2 14*ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_CORE_CLK2 3 15*ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_CORE_CLK3 4 16*ae5de77eSEmmanuel Vadot #define R9A09G056_CA55_0_PERIPHCLK 5 17*ae5de77eSEmmanuel Vadot #define R9A09G056_CM33_CLK0 6 18*ae5de77eSEmmanuel Vadot #define R9A09G056_CST_0_SWCLKTCK 7 19*ae5de77eSEmmanuel Vadot #define R9A09G056_IOTOP_0_SHCLK 8 20*ae5de77eSEmmanuel Vadot #define R9A09G056_USB2_0_CLK_CORE0 9 21*ae5de77eSEmmanuel Vadot #define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 22*ae5de77eSEmmanuel Vadot #define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 23*ae5de77eSEmmanuel Vadot 24*ae5de77eSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ 25