1*2846c905SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*2846c905SEmmanuel Vadot * 3*2846c905SEmmanuel Vadot * Copyright (C) 2024 Renesas Electronics Corp. 4*2846c905SEmmanuel Vadot */ 5*2846c905SEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ 6*2846c905SEmmanuel Vadot #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ 7*2846c905SEmmanuel Vadot 8*2846c905SEmmanuel Vadot #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*2846c905SEmmanuel Vadot 10*2846c905SEmmanuel Vadot /* Core Clock list */ 11*2846c905SEmmanuel Vadot #define R9A09G047_SYS_0_PCLK 0 12*2846c905SEmmanuel Vadot #define R9A09G047_CA55_0_CORECLK0 1 13*2846c905SEmmanuel Vadot #define R9A09G047_CA55_0_CORECLK1 2 14*2846c905SEmmanuel Vadot #define R9A09G047_CA55_0_CORECLK2 3 15*2846c905SEmmanuel Vadot #define R9A09G047_CA55_0_CORECLK3 4 16*2846c905SEmmanuel Vadot #define R9A09G047_CA55_0_PERIPHCLK 5 17*2846c905SEmmanuel Vadot #define R9A09G047_CM33_CLK0 6 18*2846c905SEmmanuel Vadot #define R9A09G047_CST_0_SWCLKTCK 7 19*2846c905SEmmanuel Vadot #define R9A09G047_IOTOP_0_SHCLK 8 20*2846c905SEmmanuel Vadot 21*2846c905SEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ 22