xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/raspberrypi,rp1-clocks.h (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa)
1*833e5d42SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*833e5d42SEmmanuel Vadot /*
3*833e5d42SEmmanuel Vadot  * Copyright (C) 2021 Raspberry Pi Ltd.
4*833e5d42SEmmanuel Vadot  */
5*833e5d42SEmmanuel Vadot 
6*833e5d42SEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
7*833e5d42SEmmanuel Vadot #define __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
8*833e5d42SEmmanuel Vadot 
9*833e5d42SEmmanuel Vadot #define RP1_PLL_SYS_CORE		0
10*833e5d42SEmmanuel Vadot #define RP1_PLL_AUDIO_CORE		1
11*833e5d42SEmmanuel Vadot #define RP1_PLL_VIDEO_CORE		2
12*833e5d42SEmmanuel Vadot 
13*833e5d42SEmmanuel Vadot #define RP1_PLL_SYS			3
14*833e5d42SEmmanuel Vadot #define RP1_PLL_AUDIO			4
15*833e5d42SEmmanuel Vadot #define RP1_PLL_VIDEO			5
16*833e5d42SEmmanuel Vadot 
17*833e5d42SEmmanuel Vadot #define RP1_PLL_SYS_PRI_PH		6
18*833e5d42SEmmanuel Vadot #define RP1_PLL_SYS_SEC_PH		7
19*833e5d42SEmmanuel Vadot #define RP1_PLL_AUDIO_PRI_PH		8
20*833e5d42SEmmanuel Vadot 
21*833e5d42SEmmanuel Vadot #define RP1_PLL_SYS_SEC			9
22*833e5d42SEmmanuel Vadot #define RP1_PLL_AUDIO_SEC		10
23*833e5d42SEmmanuel Vadot #define RP1_PLL_VIDEO_SEC		11
24*833e5d42SEmmanuel Vadot 
25*833e5d42SEmmanuel Vadot #define RP1_CLK_SYS			12
26*833e5d42SEmmanuel Vadot #define RP1_CLK_SLOW_SYS		13
27*833e5d42SEmmanuel Vadot #define RP1_CLK_DMA			14
28*833e5d42SEmmanuel Vadot #define RP1_CLK_UART			15
29*833e5d42SEmmanuel Vadot #define RP1_CLK_ETH			16
30*833e5d42SEmmanuel Vadot #define RP1_CLK_PWM0			17
31*833e5d42SEmmanuel Vadot #define RP1_CLK_PWM1			18
32*833e5d42SEmmanuel Vadot #define RP1_CLK_AUDIO_IN		19
33*833e5d42SEmmanuel Vadot #define RP1_CLK_AUDIO_OUT		20
34*833e5d42SEmmanuel Vadot #define RP1_CLK_I2S			21
35*833e5d42SEmmanuel Vadot #define RP1_CLK_MIPI0_CFG		22
36*833e5d42SEmmanuel Vadot #define RP1_CLK_MIPI1_CFG		23
37*833e5d42SEmmanuel Vadot #define RP1_CLK_PCIE_AUX		24
38*833e5d42SEmmanuel Vadot #define RP1_CLK_USBH0_MICROFRAME	25
39*833e5d42SEmmanuel Vadot #define RP1_CLK_USBH1_MICROFRAME	26
40*833e5d42SEmmanuel Vadot #define RP1_CLK_USBH0_SUSPEND		27
41*833e5d42SEmmanuel Vadot #define RP1_CLK_USBH1_SUSPEND		28
42*833e5d42SEmmanuel Vadot #define RP1_CLK_ETH_TSU			29
43*833e5d42SEmmanuel Vadot #define RP1_CLK_ADC			30
44*833e5d42SEmmanuel Vadot #define RP1_CLK_SDIO_TIMER		31
45*833e5d42SEmmanuel Vadot #define RP1_CLK_SDIO_ALT_SRC		32
46*833e5d42SEmmanuel Vadot #define RP1_CLK_GP0			33
47*833e5d42SEmmanuel Vadot #define RP1_CLK_GP1			34
48*833e5d42SEmmanuel Vadot #define RP1_CLK_GP2			35
49*833e5d42SEmmanuel Vadot #define RP1_CLK_GP3			36
50*833e5d42SEmmanuel Vadot #define RP1_CLK_GP4			37
51*833e5d42SEmmanuel Vadot #define RP1_CLK_GP5			38
52*833e5d42SEmmanuel Vadot #define RP1_CLK_VEC			39
53*833e5d42SEmmanuel Vadot #define RP1_CLK_DPI			40
54*833e5d42SEmmanuel Vadot #define RP1_CLK_MIPI0_DPI		41
55*833e5d42SEmmanuel Vadot #define RP1_CLK_MIPI1_DPI		42
56*833e5d42SEmmanuel Vadot 
57*833e5d42SEmmanuel Vadot /* Extra PLL output channels - RP1B0 only */
58*833e5d42SEmmanuel Vadot #define RP1_PLL_VIDEO_PRI_PH		43
59*833e5d42SEmmanuel Vadot #define RP1_PLL_AUDIO_TERN		44
60*833e5d42SEmmanuel Vadot 
61*833e5d42SEmmanuel Vadot #endif
62