xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/r8a77995-cpg-mssr.h (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0+
2*c66ec88fSEmmanuel Vadot  *
3*c66ec88fSEmmanuel Vadot  * Copyright (C) 2017 Glider bvba
4*c66ec88fSEmmanuel Vadot  */
5*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
6*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
7*c66ec88fSEmmanuel Vadot 
8*c66ec88fSEmmanuel Vadot #include <dt-bindings/clock/renesas-cpg-mssr.h>
9*c66ec88fSEmmanuel Vadot 
10*c66ec88fSEmmanuel Vadot /* r8a77995 CPG Core Clocks */
11*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_Z2			0
12*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_ZG			1
13*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_ZTR		2
14*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_ZT			3
15*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_ZX			4
16*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S0D1		5
17*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S1D1		6
18*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S1D2		7
19*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S1D4		8
20*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S2D1		9
21*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S2D2		10
22*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S2D4		11
23*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S3D1		12
24*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S3D2		13
25*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S3D4		14
26*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S1D4C		15
27*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S3D1C		16
28*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S3D2C		17
29*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_S3D4C		18
30*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_LB			19
31*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_CL			20
32*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_ZB3		21
33*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_ZB3D2		22
34*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_CR			23
35*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_CRD2		24
36*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_SD0H		25
37*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_SD0		26
38*c66ec88fSEmmanuel Vadot /* CLK_SSP2 was removed */
39*c66ec88fSEmmanuel Vadot /* CLK_SSP1 was removed */
40*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_RPC		29
41*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_RPCD2		30
42*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_ZA2		31
43*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_ZA8		32
44*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_Z2D		33
45*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_CANFD		34
46*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_MSO		35
47*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_R			36
48*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_OSC		37
49*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_LV0		38
50*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_LV1		39
51*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_CP			40
52*c66ec88fSEmmanuel Vadot #define R8A77995_CLK_CPEX		41
53*c66ec88fSEmmanuel Vadot 
54*c66ec88fSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
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