1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 2*c66ec88fSEmmanuel Vadot * 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2018 Renesas Electronics Corp. 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 6*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel Vadot /* r8a77470 CPG Core Clocks */ 11*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_Z2 0 12*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_ZTR 1 13*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_ZTRD2 2 14*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_ZT 3 15*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_ZX 4 16*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_ZS 5 17*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_HP 6 18*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_B 7 19*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_LB 8 20*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_P 9 21*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_CL 10 22*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_CP 11 23*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_M2 12 24*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_ZB3 13 25*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_SDH 14 26*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_SD0 15 27*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_SD1 16 28*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_SD2 17 29*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_MP 18 30*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_QSPI 19 31*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_CPEX 20 32*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_RCAN 21 33*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_R 22 34*c66ec88fSEmmanuel Vadot #define R8A77470_CLK_OSC 23 35*c66ec88fSEmmanuel Vadot 36*c66ec88fSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */ 37