1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 2*c66ec88fSEmmanuel Vadot * 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2018 Renesas Electronics Corp. 4*c66ec88fSEmmanuel Vadot * 5*c66ec88fSEmmanuel Vadot */ 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ 8*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel Vadot #include <dt-bindings/clock/renesas-cpg-mssr.h> 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel Vadot /* R7S9210 CPG Core Clocks */ 13*c66ec88fSEmmanuel Vadot #define R7S9210_CLK_I 0 14*c66ec88fSEmmanuel Vadot #define R7S9210_CLK_G 1 15*c66ec88fSEmmanuel Vadot #define R7S9210_CLK_B 2 16*c66ec88fSEmmanuel Vadot #define R7S9210_CLK_P1 3 17*c66ec88fSEmmanuel Vadot #define R7S9210_CLK_P1C 4 18*c66ec88fSEmmanuel Vadot #define R7S9210_CLK_P0 5 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */ 21