1*8d13bc63SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*8d13bc63SEmmanuel Vadot /* 3*8d13bc63SEmmanuel Vadot * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved 4*8d13bc63SEmmanuel Vadot * Copyright (c) 2023, Linaro Limited 5*8d13bc63SEmmanuel Vadot */ 6*8d13bc63SEmmanuel Vadot 7*8d13bc63SEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H 8*8d13bc63SEmmanuel Vadot #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H 9*8d13bc63SEmmanuel Vadot 10*8d13bc63SEmmanuel Vadot /* GPU_CC clocks */ 11*8d13bc63SEmmanuel Vadot #define GPU_CC_AHB_CLK 0 12*8d13bc63SEmmanuel Vadot #define GPU_CC_CRC_AHB_CLK 1 13*8d13bc63SEmmanuel Vadot #define GPU_CC_CX_ACCU_SHIFT_CLK 2 14*8d13bc63SEmmanuel Vadot #define GPU_CC_CX_FF_CLK 3 15*8d13bc63SEmmanuel Vadot #define GPU_CC_CX_GMU_CLK 4 16*8d13bc63SEmmanuel Vadot #define GPU_CC_CXO_AON_CLK 5 17*8d13bc63SEmmanuel Vadot #define GPU_CC_CXO_CLK 6 18*8d13bc63SEmmanuel Vadot #define GPU_CC_DEMET_CLK 7 19*8d13bc63SEmmanuel Vadot #define GPU_CC_DPM_CLK 8 20*8d13bc63SEmmanuel Vadot #define GPU_CC_FF_CLK_SRC 9 21*8d13bc63SEmmanuel Vadot #define GPU_CC_FREQ_MEASURE_CLK 10 22*8d13bc63SEmmanuel Vadot #define GPU_CC_GMU_CLK_SRC 11 23*8d13bc63SEmmanuel Vadot #define GPU_CC_GX_ACCU_SHIFT_CLK 12 24*8d13bc63SEmmanuel Vadot #define GPU_CC_GX_FF_CLK 13 25*8d13bc63SEmmanuel Vadot #define GPU_CC_GX_GFX3D_CLK 14 26*8d13bc63SEmmanuel Vadot #define GPU_CC_GX_GFX3D_RDVM_CLK 15 27*8d13bc63SEmmanuel Vadot #define GPU_CC_GX_GMU_CLK 16 28*8d13bc63SEmmanuel Vadot #define GPU_CC_GX_VSENSE_CLK 17 29*8d13bc63SEmmanuel Vadot #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18 30*8d13bc63SEmmanuel Vadot #define GPU_CC_HUB_AON_CLK 19 31*8d13bc63SEmmanuel Vadot #define GPU_CC_HUB_CLK_SRC 20 32*8d13bc63SEmmanuel Vadot #define GPU_CC_HUB_CX_INT_CLK 21 33*8d13bc63SEmmanuel Vadot #define GPU_CC_HUB_DIV_CLK_SRC 22 34*8d13bc63SEmmanuel Vadot #define GPU_CC_MEMNOC_GFX_CLK 23 35*8d13bc63SEmmanuel Vadot #define GPU_CC_PLL0 24 36*8d13bc63SEmmanuel Vadot #define GPU_CC_PLL1 25 37*8d13bc63SEmmanuel Vadot #define GPU_CC_SLEEP_CLK 26 38*8d13bc63SEmmanuel Vadot 39*8d13bc63SEmmanuel Vadot /* GDSCs */ 40*8d13bc63SEmmanuel Vadot #define GPU_GX_GDSC 0 41*8d13bc63SEmmanuel Vadot #define GPU_CX_GDSC 1 42*8d13bc63SEmmanuel Vadot 43*8d13bc63SEmmanuel Vadot #endif 44