1*5f62a964SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*5f62a964SEmmanuel Vadot /* 3*5f62a964SEmmanuel Vadot * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved 4*5f62a964SEmmanuel Vadot * Copyright (c) 2024, Linaro Limited 5*5f62a964SEmmanuel Vadot */ 6*5f62a964SEmmanuel Vadot 7*5f62a964SEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H 8*5f62a964SEmmanuel Vadot #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H 9*5f62a964SEmmanuel Vadot 10*5f62a964SEmmanuel Vadot /* GPU_CC clocks */ 11*5f62a964SEmmanuel Vadot #define GPU_CC_AHB_CLK 0 12*5f62a964SEmmanuel Vadot #define GPU_CC_CRC_AHB_CLK 1 13*5f62a964SEmmanuel Vadot #define GPU_CC_CX_FF_CLK 2 14*5f62a964SEmmanuel Vadot #define GPU_CC_CX_GMU_CLK 3 15*5f62a964SEmmanuel Vadot #define GPU_CC_CXO_AON_CLK 4 16*5f62a964SEmmanuel Vadot #define GPU_CC_CXO_CLK 5 17*5f62a964SEmmanuel Vadot #define GPU_CC_FF_CLK_SRC 6 18*5f62a964SEmmanuel Vadot #define GPU_CC_GMU_CLK_SRC 7 19*5f62a964SEmmanuel Vadot #define GPU_CC_GX_GMU_CLK 8 20*5f62a964SEmmanuel Vadot #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 9 21*5f62a964SEmmanuel Vadot #define GPU_CC_HUB_AON_CLK 10 22*5f62a964SEmmanuel Vadot #define GPU_CC_HUB_CLK_SRC 11 23*5f62a964SEmmanuel Vadot #define GPU_CC_HUB_CX_INT_CLK 12 24*5f62a964SEmmanuel Vadot #define GPU_CC_MEMNOC_GFX_CLK 13 25*5f62a964SEmmanuel Vadot #define GPU_CC_PLL0 14 26*5f62a964SEmmanuel Vadot #define GPU_CC_PLL1 15 27*5f62a964SEmmanuel Vadot #define GPU_CC_SLEEP_CLK 16 28*5f62a964SEmmanuel Vadot 29*5f62a964SEmmanuel Vadot /* GDSCs */ 30*5f62a964SEmmanuel Vadot #define GPU_GX_GDSC 0 31*5f62a964SEmmanuel Vadot #define GPU_CX_GDSC 1 32*5f62a964SEmmanuel Vadot 33*5f62a964SEmmanuel Vadot #endif 34