xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/qcom,milos-gpucc.h (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa)
1*833e5d42SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*833e5d42SEmmanuel Vadot /*
3*833e5d42SEmmanuel Vadot  * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4*833e5d42SEmmanuel Vadot  * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
5*833e5d42SEmmanuel Vadot  */
6*833e5d42SEmmanuel Vadot 
7*833e5d42SEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_MILOS_H
8*833e5d42SEmmanuel Vadot #define _DT_BINDINGS_CLK_QCOM_GPU_CC_MILOS_H
9*833e5d42SEmmanuel Vadot 
10*833e5d42SEmmanuel Vadot /* GPU_CC clocks */
11*833e5d42SEmmanuel Vadot #define GPU_CC_PLL0						0
12*833e5d42SEmmanuel Vadot #define GPU_CC_PLL0_OUT_EVEN					1
13*833e5d42SEmmanuel Vadot #define GPU_CC_AHB_CLK						2
14*833e5d42SEmmanuel Vadot #define GPU_CC_CB_CLK						3
15*833e5d42SEmmanuel Vadot #define GPU_CC_CX_ACCU_SHIFT_CLK				4
16*833e5d42SEmmanuel Vadot #define GPU_CC_CX_FF_CLK					5
17*833e5d42SEmmanuel Vadot #define GPU_CC_CX_GMU_CLK					6
18*833e5d42SEmmanuel Vadot #define GPU_CC_CXO_AON_CLK					7
19*833e5d42SEmmanuel Vadot #define GPU_CC_CXO_CLK						8
20*833e5d42SEmmanuel Vadot #define GPU_CC_DEMET_CLK					9
21*833e5d42SEmmanuel Vadot #define GPU_CC_DEMET_DIV_CLK_SRC				10
22*833e5d42SEmmanuel Vadot #define GPU_CC_DPM_CLK						11
23*833e5d42SEmmanuel Vadot #define GPU_CC_FF_CLK_SRC					12
24*833e5d42SEmmanuel Vadot #define GPU_CC_FREQ_MEASURE_CLK					13
25*833e5d42SEmmanuel Vadot #define GPU_CC_GMU_CLK_SRC					14
26*833e5d42SEmmanuel Vadot #define GPU_CC_GX_ACCU_SHIFT_CLK				15
27*833e5d42SEmmanuel Vadot #define GPU_CC_GX_ACD_AHB_FF_CLK				16
28*833e5d42SEmmanuel Vadot #define GPU_CC_GX_AHB_FF_CLK					17
29*833e5d42SEmmanuel Vadot #define GPU_CC_GX_GMU_CLK					18
30*833e5d42SEmmanuel Vadot #define GPU_CC_GX_RCG_AHB_FF_CLK				19
31*833e5d42SEmmanuel Vadot #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK				20
32*833e5d42SEmmanuel Vadot #define GPU_CC_HUB_AON_CLK					21
33*833e5d42SEmmanuel Vadot #define GPU_CC_HUB_CLK_SRC					22
34*833e5d42SEmmanuel Vadot #define GPU_CC_HUB_CX_INT_CLK					23
35*833e5d42SEmmanuel Vadot #define GPU_CC_HUB_DIV_CLK_SRC					24
36*833e5d42SEmmanuel Vadot #define GPU_CC_MEMNOC_GFX_CLK					25
37*833e5d42SEmmanuel Vadot #define GPU_CC_RSCC_HUB_AON_CLK					26
38*833e5d42SEmmanuel Vadot #define GPU_CC_RSCC_XO_AON_CLK					27
39*833e5d42SEmmanuel Vadot #define GPU_CC_SLEEP_CLK					28
40*833e5d42SEmmanuel Vadot #define GPU_CC_XO_CLK_SRC					29
41*833e5d42SEmmanuel Vadot #define GPU_CC_XO_DIV_CLK_SRC					30
42*833e5d42SEmmanuel Vadot 
43*833e5d42SEmmanuel Vadot /* GPU_CC resets */
44*833e5d42SEmmanuel Vadot #define GPU_CC_CB_BCR						0
45*833e5d42SEmmanuel Vadot #define GPU_CC_CX_BCR						1
46*833e5d42SEmmanuel Vadot #define GPU_CC_FAST_HUB_BCR					2
47*833e5d42SEmmanuel Vadot #define GPU_CC_FF_BCR						3
48*833e5d42SEmmanuel Vadot #define GPU_CC_GMU_BCR						4
49*833e5d42SEmmanuel Vadot #define GPU_CC_GX_BCR						5
50*833e5d42SEmmanuel Vadot #define GPU_CC_RBCPR_BCR					6
51*833e5d42SEmmanuel Vadot #define GPU_CC_XO_BCR						7
52*833e5d42SEmmanuel Vadot 
53*833e5d42SEmmanuel Vadot /* GPU_CC power domains */
54*833e5d42SEmmanuel Vadot #define GPU_CC_CX_GDSC						0
55*833e5d42SEmmanuel Vadot 
56*833e5d42SEmmanuel Vadot #endif
57