1c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2c66ec88fSEmmanuel Vadot /* 3c66ec88fSEmmanuel Vadot * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4c66ec88fSEmmanuel Vadot */ 5c66ec88fSEmmanuel Vadot 6c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H 7c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H 8c66ec88fSEmmanuel Vadot 9c66ec88fSEmmanuel Vadot #define GCC_APSS_AHB_CLK_SRC 0 10c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 11c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 12c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 13c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 14c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 15c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 16c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 17c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 18c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 19c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 20c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART0_APPS_CLK_SRC 11 21c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART1_APPS_CLK_SRC 12 22c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART2_APPS_CLK_SRC 13 23c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART3_APPS_CLK_SRC 14 24c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 25c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 26c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART0_APPS_CLK_SRC 17 27c66ec88fSEmmanuel Vadot #define GCC_BYTE0_CLK_SRC 18 28c66ec88fSEmmanuel Vadot #define GCC_EMAC_CLK_SRC 19 29c66ec88fSEmmanuel Vadot #define GCC_EMAC_PTP_CLK_SRC 20 30c66ec88fSEmmanuel Vadot #define GCC_ESC0_CLK_SRC 21 31c66ec88fSEmmanuel Vadot #define GCC_APSS_AHB_CLK 22 32c66ec88fSEmmanuel Vadot #define GCC_APSS_AXI_CLK 23 33c66ec88fSEmmanuel Vadot #define GCC_BIMC_APSS_AXI_CLK 24 34c66ec88fSEmmanuel Vadot #define GCC_BIMC_GFX_CLK 25 35c66ec88fSEmmanuel Vadot #define GCC_BIMC_MDSS_CLK 26 36c66ec88fSEmmanuel Vadot #define GCC_BLSP1_AHB_CLK 27 37c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 38c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 39c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 40c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 41c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 42c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 43c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 44c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 45c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 46c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 47c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART0_APPS_CLK 38 48c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART1_APPS_CLK 39 49c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART2_APPS_CLK 40 50c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART3_APPS_CLK 41 51c66ec88fSEmmanuel Vadot #define GCC_BLSP2_AHB_CLK 42 52c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 53c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 54c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART0_APPS_CLK 45 55c66ec88fSEmmanuel Vadot #define GCC_BOOT_ROM_AHB_CLK 46 56c66ec88fSEmmanuel Vadot #define GCC_DCC_CLK 47 57c66ec88fSEmmanuel Vadot #define GCC_GENI_IR_H_CLK 48 58c66ec88fSEmmanuel Vadot #define GCC_ETH_AXI_CLK 49 59c66ec88fSEmmanuel Vadot #define GCC_ETH_PTP_CLK 50 60c66ec88fSEmmanuel Vadot #define GCC_ETH_RGMII_CLK 51 61c66ec88fSEmmanuel Vadot #define GCC_ETH_SLAVE_AHB_CLK 52 62c66ec88fSEmmanuel Vadot #define GCC_GENI_IR_S_CLK 53 63c66ec88fSEmmanuel Vadot #define GCC_GP1_CLK 54 64c66ec88fSEmmanuel Vadot #define GCC_GP2_CLK 55 65c66ec88fSEmmanuel Vadot #define GCC_GP3_CLK 56 66c66ec88fSEmmanuel Vadot #define GCC_MDSS_AHB_CLK 57 67c66ec88fSEmmanuel Vadot #define GCC_MDSS_AXI_CLK 58 68c66ec88fSEmmanuel Vadot #define GCC_MDSS_BYTE0_CLK 59 69c66ec88fSEmmanuel Vadot #define GCC_MDSS_ESC0_CLK 60 70c66ec88fSEmmanuel Vadot #define GCC_MDSS_HDMI_APP_CLK 61 71c66ec88fSEmmanuel Vadot #define GCC_MDSS_HDMI_PCLK_CLK 62 72c66ec88fSEmmanuel Vadot #define GCC_MDSS_MDP_CLK 63 73c66ec88fSEmmanuel Vadot #define GCC_MDSS_PCLK0_CLK 64 74c66ec88fSEmmanuel Vadot #define GCC_MDSS_VSYNC_CLK 65 75c66ec88fSEmmanuel Vadot #define GCC_OXILI_AHB_CLK 66 76c66ec88fSEmmanuel Vadot #define GCC_OXILI_GFX3D_CLK 67 77c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_AUX_CLK 68 78c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_CFG_AHB_CLK 69 79c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_MSTR_AXI_CLK 70 80c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_PIPE_CLK 71 81c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_SLV_AXI_CLK 72 82c66ec88fSEmmanuel Vadot #define GCC_PCNOC_USB2_CLK 73 83c66ec88fSEmmanuel Vadot #define GCC_PCNOC_USB3_CLK 74 84c66ec88fSEmmanuel Vadot #define GCC_PDM2_CLK 75 85c66ec88fSEmmanuel Vadot #define GCC_PDM_AHB_CLK 76 86c66ec88fSEmmanuel Vadot #define GCC_VSYNC_CLK_SRC 77 87c66ec88fSEmmanuel Vadot #define GCC_PRNG_AHB_CLK 78 88c66ec88fSEmmanuel Vadot #define GCC_PWM0_XO512_CLK 79 89c66ec88fSEmmanuel Vadot #define GCC_PWM1_XO512_CLK 80 90c66ec88fSEmmanuel Vadot #define GCC_PWM2_XO512_CLK 81 91c66ec88fSEmmanuel Vadot #define GCC_SDCC1_AHB_CLK 82 92c66ec88fSEmmanuel Vadot #define GCC_SDCC1_APPS_CLK 83 93c66ec88fSEmmanuel Vadot #define GCC_SDCC1_ICE_CORE_CLK 84 94c66ec88fSEmmanuel Vadot #define GCC_SDCC2_AHB_CLK 85 95c66ec88fSEmmanuel Vadot #define GCC_SDCC2_APPS_CLK 86 96c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_USB3_CLK 87 97c66ec88fSEmmanuel Vadot #define GCC_USB20_MOCK_UTMI_CLK 88 98c66ec88fSEmmanuel Vadot #define GCC_USB2A_PHY_SLEEP_CLK 89 99c66ec88fSEmmanuel Vadot #define GCC_USB30_MASTER_CLK 90 100c66ec88fSEmmanuel Vadot #define GCC_USB30_MOCK_UTMI_CLK 91 101c66ec88fSEmmanuel Vadot #define GCC_USB30_SLEEP_CLK 92 102c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_AUX_CLK 93 103c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_PIPE_CLK 94 104c66ec88fSEmmanuel Vadot #define GCC_USB_HS_PHY_CFG_AHB_CLK 95 105c66ec88fSEmmanuel Vadot #define GCC_USB_HS_SYSTEM_CLK 96 106c66ec88fSEmmanuel Vadot #define GCC_GFX3D_CLK_SRC 97 107c66ec88fSEmmanuel Vadot #define GCC_GP1_CLK_SRC 98 108c66ec88fSEmmanuel Vadot #define GCC_GP2_CLK_SRC 99 109c66ec88fSEmmanuel Vadot #define GCC_GP3_CLK_SRC 100 110c66ec88fSEmmanuel Vadot #define GCC_GPLL0_OUT_MAIN 101 111c66ec88fSEmmanuel Vadot #define GCC_GPLL1_OUT_MAIN 102 112c66ec88fSEmmanuel Vadot #define GCC_GPLL3_OUT_MAIN 103 113c66ec88fSEmmanuel Vadot #define GCC_GPLL4_OUT_MAIN 104 114c66ec88fSEmmanuel Vadot #define GCC_HDMI_APP_CLK_SRC 105 115c66ec88fSEmmanuel Vadot #define GCC_HDMI_PCLK_CLK_SRC 106 116c66ec88fSEmmanuel Vadot #define GCC_MDP_CLK_SRC 107 117c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_AUX_CLK_SRC 108 118c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_PIPE_CLK_SRC 109 119c66ec88fSEmmanuel Vadot #define GCC_PCLK0_CLK_SRC 110 120c66ec88fSEmmanuel Vadot #define GCC_PDM2_CLK_SRC 111 121c66ec88fSEmmanuel Vadot #define GCC_SDCC1_APPS_CLK_SRC 112 122c66ec88fSEmmanuel Vadot #define GCC_SDCC1_ICE_CORE_CLK_SRC 113 123c66ec88fSEmmanuel Vadot #define GCC_SDCC2_APPS_CLK_SRC 114 124c66ec88fSEmmanuel Vadot #define GCC_USB20_MOCK_UTMI_CLK_SRC 115 125c66ec88fSEmmanuel Vadot #define GCC_USB30_MASTER_CLK_SRC 116 126c66ec88fSEmmanuel Vadot #define GCC_USB30_MOCK_UTMI_CLK_SRC 117 127c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_AUX_CLK_SRC 118 128c66ec88fSEmmanuel Vadot #define GCC_USB_HS_SYSTEM_CLK_SRC 119 129c66ec88fSEmmanuel Vadot #define GCC_GPLL0_AO_CLK_SRC 120 130c66ec88fSEmmanuel Vadot #define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 131c66ec88fSEmmanuel Vadot #define GCC_GPLL0_AO_OUT_MAIN 123 132c66ec88fSEmmanuel Vadot #define GCC_GPLL0_SLEEP_CLK_SRC 124 133c66ec88fSEmmanuel Vadot #define GCC_GPLL6 125 134c66ec88fSEmmanuel Vadot #define GCC_GPLL6_OUT_AUX 126 135c66ec88fSEmmanuel Vadot #define GCC_MDSS_MDP_VOTE_CLK 127 136c66ec88fSEmmanuel Vadot #define GCC_MDSS_ROTATOR_VOTE_CLK 128 137c66ec88fSEmmanuel Vadot #define GCC_BIMC_GPU_CLK 129 138c66ec88fSEmmanuel Vadot #define GCC_GTCU_AHB_CLK 130 139c66ec88fSEmmanuel Vadot #define GCC_GFX_TCU_CLK 131 140c66ec88fSEmmanuel Vadot #define GCC_GFX_TBU_CLK 132 141c66ec88fSEmmanuel Vadot #define GCC_SMMU_CFG_CLK 133 142c66ec88fSEmmanuel Vadot #define GCC_APSS_TCU_CLK 134 143c66ec88fSEmmanuel Vadot #define GCC_CRYPTO_AHB_CLK 135 144c66ec88fSEmmanuel Vadot #define GCC_CRYPTO_AXI_CLK 136 145c66ec88fSEmmanuel Vadot #define GCC_CRYPTO_CLK 137 146c66ec88fSEmmanuel Vadot #define GCC_MDP_TBU_CLK 138 147c66ec88fSEmmanuel Vadot #define GCC_QDSS_DAP_CLK 139 148c66ec88fSEmmanuel Vadot #define GCC_DCC_XO_CLK 140 149c66ec88fSEmmanuel Vadot #define GCC_WCSS_Q6_AHB_CLK 141 150c66ec88fSEmmanuel Vadot #define GCC_WCSS_Q6_AXIM_CLK 142 151c66ec88fSEmmanuel Vadot #define GCC_CDSP_CFG_AHB_CLK 143 152c66ec88fSEmmanuel Vadot #define GCC_BIMC_CDSP_CLK 144 153c66ec88fSEmmanuel Vadot #define GCC_CDSP_TBU_CLK 145 154c66ec88fSEmmanuel Vadot #define GCC_CDSP_BIMC_CLK_SRC 146 155c66ec88fSEmmanuel Vadot 156c66ec88fSEmmanuel Vadot #define GCC_GENI_IR_BCR 0 157c66ec88fSEmmanuel Vadot #define GCC_USB_HS_BCR 1 158c66ec88fSEmmanuel Vadot #define GCC_USB2_HS_PHY_ONLY_BCR 2 159c66ec88fSEmmanuel Vadot #define GCC_QUSB2_PHY_BCR 3 160c66ec88fSEmmanuel Vadot #define GCC_USB_HS_PHY_CFG_AHB_BCR 4 161c66ec88fSEmmanuel Vadot #define GCC_USB2A_PHY_BCR 5 162c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_BCR 6 163c66ec88fSEmmanuel Vadot #define GCC_USB_30_BCR 7 164c66ec88fSEmmanuel Vadot #define GCC_USB3PHY_PHY_BCR 8 165c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_BCR 9 166c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_PHY_BCR 10 167c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_LINK_DOWN_BCR 11 168c66ec88fSEmmanuel Vadot #define GCC_PCIEPHY_0_PHY_BCR 12 169c66ec88fSEmmanuel Vadot #define GCC_EMAC_BCR 13 170c66ec88fSEmmanuel Vadot #define GCC_CDSP_RESTART 14 171c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 172c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_AHB_ARES 16 173c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_AXI_SLAVE_ARES 17 174c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_AXI_MASTER_ARES 18 175c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_CORE_STICKY_ARES 19 176c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_SLEEP_ARES 20 177c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_PIPE_ARES 21 178c66ec88fSEmmanuel Vadot #define GCC_WDSP_RESTART 22 179c66ec88fSEmmanuel Vadot 180*cb7aa33aSEmmanuel Vadot /* Indexes for GDSCs */ 181*cb7aa33aSEmmanuel Vadot #define MDSS_GDSC 0 182*cb7aa33aSEmmanuel Vadot #define OXILI_GDSC 1 183*cb7aa33aSEmmanuel Vadot 184c66ec88fSEmmanuel Vadot #endif 185