1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H 7*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLK_MSM_GCC_8996_H 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot #define GPLL0_EARLY 0 10*c66ec88fSEmmanuel Vadot #define GPLL0 1 11*c66ec88fSEmmanuel Vadot #define GPLL1_EARLY 2 12*c66ec88fSEmmanuel Vadot #define GPLL1 3 13*c66ec88fSEmmanuel Vadot #define GPLL2_EARLY 4 14*c66ec88fSEmmanuel Vadot #define GPLL2 5 15*c66ec88fSEmmanuel Vadot #define GPLL3_EARLY 6 16*c66ec88fSEmmanuel Vadot #define GPLL3 7 17*c66ec88fSEmmanuel Vadot #define GPLL4_EARLY 8 18*c66ec88fSEmmanuel Vadot #define GPLL4 9 19*c66ec88fSEmmanuel Vadot #define SYSTEM_NOC_CLK_SRC 10 20*c66ec88fSEmmanuel Vadot #define CONFIG_NOC_CLK_SRC 11 21*c66ec88fSEmmanuel Vadot #define PERIPH_NOC_CLK_SRC 12 22*c66ec88fSEmmanuel Vadot #define MMSS_BIMC_GFX_CLK_SRC 13 23*c66ec88fSEmmanuel Vadot #define USB30_MASTER_CLK_SRC 14 24*c66ec88fSEmmanuel Vadot #define USB30_MOCK_UTMI_CLK_SRC 15 25*c66ec88fSEmmanuel Vadot #define USB3_PHY_AUX_CLK_SRC 16 26*c66ec88fSEmmanuel Vadot #define USB20_MASTER_CLK_SRC 17 27*c66ec88fSEmmanuel Vadot #define USB20_MOCK_UTMI_CLK_SRC 18 28*c66ec88fSEmmanuel Vadot #define SDCC1_APPS_CLK_SRC 19 29*c66ec88fSEmmanuel Vadot #define SDCC1_ICE_CORE_CLK_SRC 20 30*c66ec88fSEmmanuel Vadot #define SDCC2_APPS_CLK_SRC 21 31*c66ec88fSEmmanuel Vadot #define SDCC3_APPS_CLK_SRC 22 32*c66ec88fSEmmanuel Vadot #define SDCC4_APPS_CLK_SRC 23 33*c66ec88fSEmmanuel Vadot #define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 34*c66ec88fSEmmanuel Vadot #define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 35*c66ec88fSEmmanuel Vadot #define BLSP1_UART1_APPS_CLK_SRC 26 36*c66ec88fSEmmanuel Vadot #define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 37*c66ec88fSEmmanuel Vadot #define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 38*c66ec88fSEmmanuel Vadot #define BLSP1_UART2_APPS_CLK_SRC 29 39*c66ec88fSEmmanuel Vadot #define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 40*c66ec88fSEmmanuel Vadot #define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 41*c66ec88fSEmmanuel Vadot #define BLSP1_UART3_APPS_CLK_SRC 32 42*c66ec88fSEmmanuel Vadot #define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 43*c66ec88fSEmmanuel Vadot #define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 44*c66ec88fSEmmanuel Vadot #define BLSP1_UART4_APPS_CLK_SRC 35 45*c66ec88fSEmmanuel Vadot #define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 46*c66ec88fSEmmanuel Vadot #define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 47*c66ec88fSEmmanuel Vadot #define BLSP1_UART5_APPS_CLK_SRC 38 48*c66ec88fSEmmanuel Vadot #define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 49*c66ec88fSEmmanuel Vadot #define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 50*c66ec88fSEmmanuel Vadot #define BLSP1_UART6_APPS_CLK_SRC 41 51*c66ec88fSEmmanuel Vadot #define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 52*c66ec88fSEmmanuel Vadot #define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 53*c66ec88fSEmmanuel Vadot #define BLSP2_UART1_APPS_CLK_SRC 44 54*c66ec88fSEmmanuel Vadot #define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 55*c66ec88fSEmmanuel Vadot #define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 56*c66ec88fSEmmanuel Vadot #define BLSP2_UART2_APPS_CLK_SRC 47 57*c66ec88fSEmmanuel Vadot #define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 58*c66ec88fSEmmanuel Vadot #define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 59*c66ec88fSEmmanuel Vadot #define BLSP2_UART3_APPS_CLK_SRC 50 60*c66ec88fSEmmanuel Vadot #define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 61*c66ec88fSEmmanuel Vadot #define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 62*c66ec88fSEmmanuel Vadot #define BLSP2_UART4_APPS_CLK_SRC 53 63*c66ec88fSEmmanuel Vadot #define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 64*c66ec88fSEmmanuel Vadot #define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 65*c66ec88fSEmmanuel Vadot #define BLSP2_UART5_APPS_CLK_SRC 56 66*c66ec88fSEmmanuel Vadot #define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 67*c66ec88fSEmmanuel Vadot #define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 68*c66ec88fSEmmanuel Vadot #define BLSP2_UART6_APPS_CLK_SRC 59 69*c66ec88fSEmmanuel Vadot #define PDM2_CLK_SRC 60 70*c66ec88fSEmmanuel Vadot #define TSIF_REF_CLK_SRC 61 71*c66ec88fSEmmanuel Vadot #define CE1_CLK_SRC 62 72*c66ec88fSEmmanuel Vadot #define GCC_SLEEP_CLK_SRC 63 73*c66ec88fSEmmanuel Vadot #define BIMC_CLK_SRC 64 74*c66ec88fSEmmanuel Vadot #define HMSS_AHB_CLK_SRC 65 75*c66ec88fSEmmanuel Vadot #define BIMC_HMSS_AXI_CLK_SRC 66 76*c66ec88fSEmmanuel Vadot #define HMSS_RBCPR_CLK_SRC 67 77*c66ec88fSEmmanuel Vadot #define HMSS_GPLL0_CLK_SRC 68 78*c66ec88fSEmmanuel Vadot #define GP1_CLK_SRC 69 79*c66ec88fSEmmanuel Vadot #define GP2_CLK_SRC 70 80*c66ec88fSEmmanuel Vadot #define GP3_CLK_SRC 71 81*c66ec88fSEmmanuel Vadot #define PCIE_AUX_CLK_SRC 72 82*c66ec88fSEmmanuel Vadot #define UFS_AXI_CLK_SRC 73 83*c66ec88fSEmmanuel Vadot #define UFS_ICE_CORE_CLK_SRC 74 84*c66ec88fSEmmanuel Vadot #define QSPI_SER_CLK_SRC 75 85*c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_AXI_CLK 76 86*c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_HMSS_AHB_CLK 77 87*c66ec88fSEmmanuel Vadot #define GCC_SNOC_CNOC_AHB_CLK 78 88*c66ec88fSEmmanuel Vadot #define GCC_SNOC_PNOC_AHB_CLK 79 89*c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_AT_CLK 80 90*c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_USB3_AXI_CLK 81 91*c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_UFS_AXI_CLK 82 92*c66ec88fSEmmanuel Vadot #define GCC_CFG_NOC_AHB_CLK 83 93*c66ec88fSEmmanuel Vadot #define GCC_PERIPH_NOC_AHB_CLK 84 94*c66ec88fSEmmanuel Vadot #define GCC_PERIPH_NOC_USB20_AHB_CLK 85 95*c66ec88fSEmmanuel Vadot #define GCC_TIC_CLK 86 96*c66ec88fSEmmanuel Vadot #define GCC_IMEM_AXI_CLK 87 97*c66ec88fSEmmanuel Vadot #define GCC_MMSS_SYS_NOC_AXI_CLK 88 98*c66ec88fSEmmanuel Vadot #define GCC_MMSS_NOC_CFG_AHB_CLK 89 99*c66ec88fSEmmanuel Vadot #define GCC_MMSS_BIMC_GFX_CLK 90 100*c66ec88fSEmmanuel Vadot #define GCC_USB30_MASTER_CLK 91 101*c66ec88fSEmmanuel Vadot #define GCC_USB30_SLEEP_CLK 92 102*c66ec88fSEmmanuel Vadot #define GCC_USB30_MOCK_UTMI_CLK 93 103*c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_AUX_CLK 94 104*c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_PIPE_CLK 95 105*c66ec88fSEmmanuel Vadot #define GCC_USB20_MASTER_CLK 96 106*c66ec88fSEmmanuel Vadot #define GCC_USB20_SLEEP_CLK 97 107*c66ec88fSEmmanuel Vadot #define GCC_USB20_MOCK_UTMI_CLK 98 108*c66ec88fSEmmanuel Vadot #define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 109*c66ec88fSEmmanuel Vadot #define GCC_SDCC1_APPS_CLK 100 110*c66ec88fSEmmanuel Vadot #define GCC_SDCC1_AHB_CLK 101 111*c66ec88fSEmmanuel Vadot #define GCC_SDCC1_ICE_CORE_CLK 102 112*c66ec88fSEmmanuel Vadot #define GCC_SDCC2_APPS_CLK 103 113*c66ec88fSEmmanuel Vadot #define GCC_SDCC2_AHB_CLK 104 114*c66ec88fSEmmanuel Vadot #define GCC_SDCC3_APPS_CLK 105 115*c66ec88fSEmmanuel Vadot #define GCC_SDCC3_AHB_CLK 106 116*c66ec88fSEmmanuel Vadot #define GCC_SDCC4_APPS_CLK 107 117*c66ec88fSEmmanuel Vadot #define GCC_SDCC4_AHB_CLK 108 118*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_AHB_CLK 109 119*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_SLEEP_CLK 110 120*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 121*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 122*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART1_APPS_CLK 113 123*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 124*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 125*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART2_APPS_CLK 116 126*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 127*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 128*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART3_APPS_CLK 119 129*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 130*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 131*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART4_APPS_CLK 122 132*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 133*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 134*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART5_APPS_CLK 125 135*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 136*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 137*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART6_APPS_CLK 128 138*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_AHB_CLK 129 139*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_SLEEP_CLK 130 140*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 141*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 142*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART1_APPS_CLK 133 143*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 144*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 145*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART2_APPS_CLK 136 146*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 147*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 148*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART3_APPS_CLK 139 149*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 150*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 151*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART4_APPS_CLK 142 152*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 153*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 154*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART5_APPS_CLK 145 155*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 156*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 157*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART6_APPS_CLK 148 158*c66ec88fSEmmanuel Vadot #define GCC_PDM_AHB_CLK 149 159*c66ec88fSEmmanuel Vadot #define GCC_PDM_XO4_CLK 150 160*c66ec88fSEmmanuel Vadot #define GCC_PDM2_CLK 151 161*c66ec88fSEmmanuel Vadot #define GCC_PRNG_AHB_CLK 152 162*c66ec88fSEmmanuel Vadot #define GCC_TSIF_AHB_CLK 153 163*c66ec88fSEmmanuel Vadot #define GCC_TSIF_REF_CLK 154 164*c66ec88fSEmmanuel Vadot #define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 165*c66ec88fSEmmanuel Vadot #define GCC_TCSR_AHB_CLK 156 166*c66ec88fSEmmanuel Vadot #define GCC_BOOT_ROM_AHB_CLK 157 167*c66ec88fSEmmanuel Vadot #define GCC_MSG_RAM_AHB_CLK 158 168*c66ec88fSEmmanuel Vadot #define GCC_TLMM_AHB_CLK 159 169*c66ec88fSEmmanuel Vadot #define GCC_TLMM_CLK 160 170*c66ec88fSEmmanuel Vadot #define GCC_MPM_AHB_CLK 161 171*c66ec88fSEmmanuel Vadot #define GCC_SPMI_SER_CLK 162 172*c66ec88fSEmmanuel Vadot #define GCC_SPMI_CNOC_AHB_CLK 163 173*c66ec88fSEmmanuel Vadot #define GCC_CE1_CLK 164 174*c66ec88fSEmmanuel Vadot #define GCC_CE1_AXI_CLK 165 175*c66ec88fSEmmanuel Vadot #define GCC_CE1_AHB_CLK 166 176*c66ec88fSEmmanuel Vadot #define GCC_BIMC_HMSS_AXI_CLK 167 177*c66ec88fSEmmanuel Vadot #define GCC_BIMC_GFX_CLK 168 178*c66ec88fSEmmanuel Vadot #define GCC_HMSS_AHB_CLK 169 179*c66ec88fSEmmanuel Vadot #define GCC_HMSS_SLV_AXI_CLK 170 180*c66ec88fSEmmanuel Vadot #define GCC_HMSS_MSTR_AXI_CLK 171 181*c66ec88fSEmmanuel Vadot #define GCC_HMSS_RBCPR_CLK 172 182*c66ec88fSEmmanuel Vadot #define GCC_GP1_CLK 173 183*c66ec88fSEmmanuel Vadot #define GCC_GP2_CLK 174 184*c66ec88fSEmmanuel Vadot #define GCC_GP3_CLK 175 185*c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_SLV_AXI_CLK 176 186*c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_MSTR_AXI_CLK 177 187*c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_CFG_AHB_CLK 178 188*c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_AUX_CLK 179 189*c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_PIPE_CLK 180 190*c66ec88fSEmmanuel Vadot #define GCC_PCIE_1_SLV_AXI_CLK 181 191*c66ec88fSEmmanuel Vadot #define GCC_PCIE_1_MSTR_AXI_CLK 182 192*c66ec88fSEmmanuel Vadot #define GCC_PCIE_1_CFG_AHB_CLK 183 193*c66ec88fSEmmanuel Vadot #define GCC_PCIE_1_AUX_CLK 184 194*c66ec88fSEmmanuel Vadot #define GCC_PCIE_1_PIPE_CLK 185 195*c66ec88fSEmmanuel Vadot #define GCC_PCIE_2_SLV_AXI_CLK 186 196*c66ec88fSEmmanuel Vadot #define GCC_PCIE_2_MSTR_AXI_CLK 187 197*c66ec88fSEmmanuel Vadot #define GCC_PCIE_2_CFG_AHB_CLK 188 198*c66ec88fSEmmanuel Vadot #define GCC_PCIE_2_AUX_CLK 189 199*c66ec88fSEmmanuel Vadot #define GCC_PCIE_2_PIPE_CLK 190 200*c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_CFG_AHB_CLK 191 201*c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_AUX_CLK 192 202*c66ec88fSEmmanuel Vadot #define GCC_UFS_AXI_CLK 193 203*c66ec88fSEmmanuel Vadot #define GCC_UFS_AHB_CLK 194 204*c66ec88fSEmmanuel Vadot #define GCC_UFS_TX_CFG_CLK 195 205*c66ec88fSEmmanuel Vadot #define GCC_UFS_RX_CFG_CLK 196 206*c66ec88fSEmmanuel Vadot #define GCC_UFS_TX_SYMBOL_0_CLK 197 207*c66ec88fSEmmanuel Vadot #define GCC_UFS_RX_SYMBOL_0_CLK 198 208*c66ec88fSEmmanuel Vadot #define GCC_UFS_RX_SYMBOL_1_CLK 199 209*c66ec88fSEmmanuel Vadot #define GCC_UFS_UNIPRO_CORE_CLK 200 210*c66ec88fSEmmanuel Vadot #define GCC_UFS_ICE_CORE_CLK 201 211*c66ec88fSEmmanuel Vadot #define GCC_UFS_SYS_CLK_CORE_CLK 202 212*c66ec88fSEmmanuel Vadot #define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 213*c66ec88fSEmmanuel Vadot #define GCC_AGGRE0_SNOC_AXI_CLK 204 214*c66ec88fSEmmanuel Vadot #define GCC_AGGRE0_CNOC_AHB_CLK 205 215*c66ec88fSEmmanuel Vadot #define GCC_SMMU_AGGRE0_AXI_CLK 206 216*c66ec88fSEmmanuel Vadot #define GCC_SMMU_AGGRE0_AHB_CLK 207 217*c66ec88fSEmmanuel Vadot #define GCC_AGGRE1_PNOC_AHB_CLK 208 218*c66ec88fSEmmanuel Vadot #define GCC_AGGRE2_UFS_AXI_CLK 209 219*c66ec88fSEmmanuel Vadot #define GCC_AGGRE2_USB3_AXI_CLK 210 220*c66ec88fSEmmanuel Vadot #define GCC_QSPI_AHB_CLK 211 221*c66ec88fSEmmanuel Vadot #define GCC_QSPI_SER_CLK 212 222*c66ec88fSEmmanuel Vadot #define GCC_USB3_CLKREF_CLK 213 223*c66ec88fSEmmanuel Vadot #define GCC_HDMI_CLKREF_CLK 214 224*c66ec88fSEmmanuel Vadot #define GCC_UFS_CLKREF_CLK 215 225*c66ec88fSEmmanuel Vadot #define GCC_PCIE_CLKREF_CLK 216 226*c66ec88fSEmmanuel Vadot #define GCC_RX2_USB2_CLKREF_CLK 217 227*c66ec88fSEmmanuel Vadot #define GCC_RX1_USB2_CLKREF_CLK 218 228*c66ec88fSEmmanuel Vadot #define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 229*c66ec88fSEmmanuel Vadot #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 230*c66ec88fSEmmanuel Vadot #define GCC_EDP_CLKREF_CLK 221 231*c66ec88fSEmmanuel Vadot #define GCC_MSS_CFG_AHB_CLK 222 232*c66ec88fSEmmanuel Vadot #define GCC_MSS_Q6_BIMC_AXI_CLK 223 233*c66ec88fSEmmanuel Vadot #define GCC_MSS_SNOC_AXI_CLK 224 234*c66ec88fSEmmanuel Vadot #define GCC_MSS_MNOC_BIMC_AXI_CLK 225 235*c66ec88fSEmmanuel Vadot #define GCC_DCC_AHB_CLK 226 236*c66ec88fSEmmanuel Vadot #define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 237*c66ec88fSEmmanuel Vadot #define GCC_MMSS_GPLL0_DIV_CLK 228 238*c66ec88fSEmmanuel Vadot #define GCC_MSS_GPLL0_DIV_CLK 229 239*c66ec88fSEmmanuel Vadot 240*c66ec88fSEmmanuel Vadot #define GCC_SYSTEM_NOC_BCR 0 241*c66ec88fSEmmanuel Vadot #define GCC_CONFIG_NOC_BCR 1 242*c66ec88fSEmmanuel Vadot #define GCC_PERIPH_NOC_BCR 2 243*c66ec88fSEmmanuel Vadot #define GCC_IMEM_BCR 3 244*c66ec88fSEmmanuel Vadot #define GCC_MMSS_BCR 4 245*c66ec88fSEmmanuel Vadot #define GCC_PIMEM_BCR 5 246*c66ec88fSEmmanuel Vadot #define GCC_QDSS_BCR 6 247*c66ec88fSEmmanuel Vadot #define GCC_USB_30_BCR 7 248*c66ec88fSEmmanuel Vadot #define GCC_USB_20_BCR 8 249*c66ec88fSEmmanuel Vadot #define GCC_QUSB2PHY_PRIM_BCR 9 250*c66ec88fSEmmanuel Vadot #define GCC_QUSB2PHY_SEC_BCR 10 251*c66ec88fSEmmanuel Vadot #define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 252*c66ec88fSEmmanuel Vadot #define GCC_SDCC1_BCR 12 253*c66ec88fSEmmanuel Vadot #define GCC_SDCC2_BCR 13 254*c66ec88fSEmmanuel Vadot #define GCC_SDCC3_BCR 14 255*c66ec88fSEmmanuel Vadot #define GCC_SDCC4_BCR 15 256*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_BCR 16 257*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_BCR 17 258*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART1_BCR 18 259*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_BCR 19 260*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART2_BCR 20 261*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_BCR 21 262*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART3_BCR 22 263*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_BCR 23 264*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART4_BCR 24 265*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP5_BCR 25 266*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART5_BCR 26 267*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP6_BCR 27 268*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART6_BCR 28 269*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_BCR 29 270*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP1_BCR 30 271*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART1_BCR 31 272*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP2_BCR 32 273*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART2_BCR 33 274*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP3_BCR 34 275*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART3_BCR 35 276*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP4_BCR 36 277*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART4_BCR 37 278*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP5_BCR 38 279*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART5_BCR 39 280*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP6_BCR 40 281*c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART6_BCR 41 282*c66ec88fSEmmanuel Vadot #define GCC_PDM_BCR 42 283*c66ec88fSEmmanuel Vadot #define GCC_PRNG_BCR 43 284*c66ec88fSEmmanuel Vadot #define GCC_TSIF_BCR 44 285*c66ec88fSEmmanuel Vadot #define GCC_TCSR_BCR 45 286*c66ec88fSEmmanuel Vadot #define GCC_BOOT_ROM_BCR 46 287*c66ec88fSEmmanuel Vadot #define GCC_MSG_RAM_BCR 47 288*c66ec88fSEmmanuel Vadot #define GCC_TLMM_BCR 48 289*c66ec88fSEmmanuel Vadot #define GCC_MPM_BCR 49 290*c66ec88fSEmmanuel Vadot #define GCC_SEC_CTRL_BCR 50 291*c66ec88fSEmmanuel Vadot #define GCC_SPMI_BCR 51 292*c66ec88fSEmmanuel Vadot #define GCC_SPDM_BCR 52 293*c66ec88fSEmmanuel Vadot #define GCC_CE1_BCR 53 294*c66ec88fSEmmanuel Vadot #define GCC_BIMC_BCR 54 295*c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT0_BCR 55 296*c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT2_BCR 56 297*c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT1_BCR 57 298*c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT3_BCR 58 299*c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 300*c66ec88fSEmmanuel Vadot #define GCC_PNOC_BUS_TIMEOUT0_BCR 60 301*c66ec88fSEmmanuel Vadot #define GCC_PNOC_BUS_TIMEOUT1_BCR 61 302*c66ec88fSEmmanuel Vadot #define GCC_PNOC_BUS_TIMEOUT2_BCR 62 303*c66ec88fSEmmanuel Vadot #define GCC_PNOC_BUS_TIMEOUT3_BCR 63 304*c66ec88fSEmmanuel Vadot #define GCC_PNOC_BUS_TIMEOUT4_BCR 64 305*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT0_BCR 65 306*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT1_BCR 66 307*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT2_BCR 67 308*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT3_BCR 68 309*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT4_BCR 69 310*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT5_BCR 70 311*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT6_BCR 71 312*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT7_BCR 72 313*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT8_BCR 73 314*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT9_BCR 74 315*c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 316*c66ec88fSEmmanuel Vadot #define GCC_APB2JTAG_BCR 76 317*c66ec88fSEmmanuel Vadot #define GCC_RBCPR_CX_BCR 77 318*c66ec88fSEmmanuel Vadot #define GCC_RBCPR_MX_BCR 78 319*c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_BCR 79 320*c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_PHY_BCR 80 321*c66ec88fSEmmanuel Vadot #define GCC_PCIE_1_BCR 81 322*c66ec88fSEmmanuel Vadot #define GCC_PCIE_1_PHY_BCR 82 323*c66ec88fSEmmanuel Vadot #define GCC_PCIE_2_BCR 83 324*c66ec88fSEmmanuel Vadot #define GCC_PCIE_2_PHY_BCR 84 325*c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_BCR 85 326*c66ec88fSEmmanuel Vadot #define GCC_DCD_BCR 86 327*c66ec88fSEmmanuel Vadot #define GCC_OBT_ODT_BCR 87 328*c66ec88fSEmmanuel Vadot #define GCC_UFS_BCR 88 329*c66ec88fSEmmanuel Vadot #define GCC_SSC_BCR 89 330*c66ec88fSEmmanuel Vadot #define GCC_VS_BCR 90 331*c66ec88fSEmmanuel Vadot #define GCC_AGGRE0_NOC_BCR 91 332*c66ec88fSEmmanuel Vadot #define GCC_AGGRE1_NOC_BCR 92 333*c66ec88fSEmmanuel Vadot #define GCC_AGGRE2_NOC_BCR 93 334*c66ec88fSEmmanuel Vadot #define GCC_DCC_BCR 94 335*c66ec88fSEmmanuel Vadot #define GCC_IPA_BCR 95 336*c66ec88fSEmmanuel Vadot #define GCC_QSPI_BCR 96 337*c66ec88fSEmmanuel Vadot #define GCC_SKL_BCR 97 338*c66ec88fSEmmanuel Vadot #define GCC_MSMPU_BCR 98 339*c66ec88fSEmmanuel Vadot #define GCC_MSS_Q6_BCR 99 340*c66ec88fSEmmanuel Vadot #define GCC_QREFS_VBG_CAL_BCR 100 341*c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_COM_BCR 101 342*c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_COM_NOCSR_BCR 102 343*c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_BCR 103 344*c66ec88fSEmmanuel Vadot #define GCC_USB3PHY_PHY_BCR 104 345*c66ec88fSEmmanuel Vadot #define GCC_MSS_RESTART 105 346*c66ec88fSEmmanuel Vadot 347*c66ec88fSEmmanuel Vadot 348*c66ec88fSEmmanuel Vadot /* Indexes for GDSCs */ 349*c66ec88fSEmmanuel Vadot #define AGGRE0_NOC_GDSC 0 350*c66ec88fSEmmanuel Vadot #define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 351*c66ec88fSEmmanuel Vadot #define HLOS1_VOTE_LPASS_ADSP_GDSC 2 352*c66ec88fSEmmanuel Vadot #define HLOS1_VOTE_LPASS_CORE_GDSC 3 353*c66ec88fSEmmanuel Vadot #define USB30_GDSC 4 354*c66ec88fSEmmanuel Vadot #define PCIE0_GDSC 5 355*c66ec88fSEmmanuel Vadot #define PCIE1_GDSC 6 356*c66ec88fSEmmanuel Vadot #define PCIE2_GDSC 7 357*c66ec88fSEmmanuel Vadot #define UFS_GDSC 8 358*c66ec88fSEmmanuel Vadot 359*c66ec88fSEmmanuel Vadot #endif 360