1*833e5d42SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*833e5d42SEmmanuel Vadot /* 3*833e5d42SEmmanuel Vadot * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4*833e5d42SEmmanuel Vadot */ 5*833e5d42SEmmanuel Vadot 6*833e5d42SEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H 7*833e5d42SEmmanuel Vadot #define _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H 8*833e5d42SEmmanuel Vadot 9*833e5d42SEmmanuel Vadot /* CMN PLL core clock. */ 10*833e5d42SEmmanuel Vadot #define IPQ5424_CMN_PLL_CLK 0 11*833e5d42SEmmanuel Vadot 12*833e5d42SEmmanuel Vadot /* The output clocks from CMN PLL of IPQ5424. */ 13*833e5d42SEmmanuel Vadot #define IPQ5424_XO_24MHZ_CLK 1 14*833e5d42SEmmanuel Vadot #define IPQ5424_SLEEP_32KHZ_CLK 2 15*833e5d42SEmmanuel Vadot #define IPQ5424_PCS_31P25MHZ_CLK 3 16*833e5d42SEmmanuel Vadot #define IPQ5424_NSS_300MHZ_CLK 4 17*833e5d42SEmmanuel Vadot #define IPQ5424_PPE_375MHZ_CLK 5 18*833e5d42SEmmanuel Vadot #define IPQ5424_ETH0_50MHZ_CLK 6 19*833e5d42SEmmanuel Vadot #define IPQ5424_ETH1_50MHZ_CLK 7 20*833e5d42SEmmanuel Vadot #define IPQ5424_ETH2_50MHZ_CLK 8 21*833e5d42SEmmanuel Vadot #define IPQ5424_ETH_25MHZ_CLK 9 22*833e5d42SEmmanuel Vadot #endif 23