1*2846c905SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*2846c905SEmmanuel Vadot /* 3*2846c905SEmmanuel Vadot * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4*2846c905SEmmanuel Vadot */ 5*2846c905SEmmanuel Vadot 6*2846c905SEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H 7*2846c905SEmmanuel Vadot #define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H 8*2846c905SEmmanuel Vadot 9*2846c905SEmmanuel Vadot /* CMN PLL core clock. */ 10*2846c905SEmmanuel Vadot #define CMN_PLL_CLK 0 11*2846c905SEmmanuel Vadot 12*2846c905SEmmanuel Vadot /* The output clocks from CMN PLL of IPQ9574. */ 13*2846c905SEmmanuel Vadot #define XO_24MHZ_CLK 1 14*2846c905SEmmanuel Vadot #define SLEEP_32KHZ_CLK 2 15*2846c905SEmmanuel Vadot #define PCS_31P25MHZ_CLK 3 16*2846c905SEmmanuel Vadot #define NSS_1200MHZ_CLK 4 17*2846c905SEmmanuel Vadot #define PPE_353MHZ_CLK 5 18*2846c905SEmmanuel Vadot #define ETH0_50MHZ_CLK 6 19*2846c905SEmmanuel Vadot #define ETH1_50MHZ_CLK 7 20*2846c905SEmmanuel Vadot #define ETH2_50MHZ_CLK 8 21*2846c905SEmmanuel Vadot #define ETH_25MHZ_CLK 9 22*2846c905SEmmanuel Vadot #endif 23