xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/qcom,gcc-msm8998.h (revision b2d2a78ad80ec68d4a17f5aef97d21686cb1e29b)
1c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */
2c66ec88fSEmmanuel Vadot /*
3c66ec88fSEmmanuel Vadot  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
4c66ec88fSEmmanuel Vadot  */
5c66ec88fSEmmanuel Vadot 
6c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
7c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
8c66ec88fSEmmanuel Vadot 
9c66ec88fSEmmanuel Vadot #define BLSP1_QUP1_I2C_APPS_CLK_SRC				0
10c66ec88fSEmmanuel Vadot #define BLSP1_QUP1_SPI_APPS_CLK_SRC				1
11c66ec88fSEmmanuel Vadot #define BLSP1_QUP2_I2C_APPS_CLK_SRC				2
12c66ec88fSEmmanuel Vadot #define BLSP1_QUP2_SPI_APPS_CLK_SRC				3
13c66ec88fSEmmanuel Vadot #define BLSP1_QUP3_I2C_APPS_CLK_SRC				4
14c66ec88fSEmmanuel Vadot #define BLSP1_QUP3_SPI_APPS_CLK_SRC				5
15c66ec88fSEmmanuel Vadot #define BLSP1_QUP4_I2C_APPS_CLK_SRC				6
16c66ec88fSEmmanuel Vadot #define BLSP1_QUP4_SPI_APPS_CLK_SRC				7
17c66ec88fSEmmanuel Vadot #define BLSP1_QUP5_I2C_APPS_CLK_SRC				8
18c66ec88fSEmmanuel Vadot #define BLSP1_QUP5_SPI_APPS_CLK_SRC				9
19c66ec88fSEmmanuel Vadot #define BLSP1_QUP6_I2C_APPS_CLK_SRC				10
20c66ec88fSEmmanuel Vadot #define BLSP1_QUP6_SPI_APPS_CLK_SRC				11
21c66ec88fSEmmanuel Vadot #define BLSP1_UART1_APPS_CLK_SRC				12
22c66ec88fSEmmanuel Vadot #define BLSP1_UART2_APPS_CLK_SRC				13
23c66ec88fSEmmanuel Vadot #define BLSP1_UART3_APPS_CLK_SRC				14
24c66ec88fSEmmanuel Vadot #define BLSP2_QUP1_I2C_APPS_CLK_SRC				15
25c66ec88fSEmmanuel Vadot #define BLSP2_QUP1_SPI_APPS_CLK_SRC				16
26c66ec88fSEmmanuel Vadot #define BLSP2_QUP2_I2C_APPS_CLK_SRC				17
27c66ec88fSEmmanuel Vadot #define BLSP2_QUP2_SPI_APPS_CLK_SRC				18
28c66ec88fSEmmanuel Vadot #define BLSP2_QUP3_I2C_APPS_CLK_SRC				19
29c66ec88fSEmmanuel Vadot #define BLSP2_QUP3_SPI_APPS_CLK_SRC				20
30c66ec88fSEmmanuel Vadot #define BLSP2_QUP4_I2C_APPS_CLK_SRC				21
31c66ec88fSEmmanuel Vadot #define BLSP2_QUP4_SPI_APPS_CLK_SRC				22
32c66ec88fSEmmanuel Vadot #define BLSP2_QUP5_I2C_APPS_CLK_SRC				23
33c66ec88fSEmmanuel Vadot #define BLSP2_QUP5_SPI_APPS_CLK_SRC				24
34c66ec88fSEmmanuel Vadot #define BLSP2_QUP6_I2C_APPS_CLK_SRC				25
35c66ec88fSEmmanuel Vadot #define BLSP2_QUP6_SPI_APPS_CLK_SRC				26
36c66ec88fSEmmanuel Vadot #define BLSP2_UART1_APPS_CLK_SRC				27
37c66ec88fSEmmanuel Vadot #define BLSP2_UART2_APPS_CLK_SRC				28
38c66ec88fSEmmanuel Vadot #define BLSP2_UART3_APPS_CLK_SRC				29
39c66ec88fSEmmanuel Vadot #define GCC_AGGRE1_NOC_XO_CLK					30
40c66ec88fSEmmanuel Vadot #define GCC_AGGRE1_UFS_AXI_CLK					31
41c66ec88fSEmmanuel Vadot #define GCC_AGGRE1_USB3_AXI_CLK					32
42c66ec88fSEmmanuel Vadot #define GCC_APSS_QDSS_TSCTR_DIV2_CLK				33
43c66ec88fSEmmanuel Vadot #define GCC_APSS_QDSS_TSCTR_DIV8_CLK				34
44c66ec88fSEmmanuel Vadot #define GCC_BIMC_HMSS_AXI_CLK					35
45c66ec88fSEmmanuel Vadot #define GCC_BIMC_MSS_Q6_AXI_CLK					36
46c66ec88fSEmmanuel Vadot #define GCC_BLSP1_AHB_CLK					37
47c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_I2C_APPS_CLK				38
48c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_SPI_APPS_CLK				39
49c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_I2C_APPS_CLK				40
50c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_SPI_APPS_CLK				41
51c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_I2C_APPS_CLK				42
52c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_SPI_APPS_CLK				43
53c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_I2C_APPS_CLK				44
54c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_SPI_APPS_CLK				45
55c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP5_I2C_APPS_CLK				46
56c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP5_SPI_APPS_CLK				47
57c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP6_I2C_APPS_CLK				48
58c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP6_SPI_APPS_CLK				49
59c66ec88fSEmmanuel Vadot #define GCC_BLSP1_SLEEP_CLK					50
60c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART1_APPS_CLK				51
61c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART2_APPS_CLK				52
62c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART3_APPS_CLK				53
63c66ec88fSEmmanuel Vadot #define GCC_BLSP2_AHB_CLK					54
64c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP1_I2C_APPS_CLK				55
65c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP1_SPI_APPS_CLK				56
66c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP2_I2C_APPS_CLK				57
67c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP2_SPI_APPS_CLK				58
68c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP3_I2C_APPS_CLK				59
69c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP3_SPI_APPS_CLK				60
70c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP4_I2C_APPS_CLK				61
71c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP4_SPI_APPS_CLK				62
72c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP5_I2C_APPS_CLK				63
73c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP5_SPI_APPS_CLK				64
74c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP6_I2C_APPS_CLK				65
75c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP6_SPI_APPS_CLK				66
76c66ec88fSEmmanuel Vadot #define GCC_BLSP2_SLEEP_CLK					67
77c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART1_APPS_CLK				68
78c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART2_APPS_CLK				69
79c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART3_APPS_CLK				70
80c66ec88fSEmmanuel Vadot #define GCC_CFG_NOC_USB3_AXI_CLK				71
81c66ec88fSEmmanuel Vadot #define GCC_GP1_CLK						72
82c66ec88fSEmmanuel Vadot #define GCC_GP2_CLK						73
83c66ec88fSEmmanuel Vadot #define GCC_GP3_CLK						74
84c66ec88fSEmmanuel Vadot #define GCC_GPU_BIMC_GFX_CLK					75
85c66ec88fSEmmanuel Vadot #define GCC_GPU_BIMC_GFX_SRC_CLK				76
86c66ec88fSEmmanuel Vadot #define GCC_GPU_CFG_AHB_CLK					77
87c66ec88fSEmmanuel Vadot #define GCC_GPU_SNOC_DVM_GFX_CLK				78
88c66ec88fSEmmanuel Vadot #define GCC_HMSS_AHB_CLK					79
89c66ec88fSEmmanuel Vadot #define GCC_HMSS_AT_CLK						80
90c66ec88fSEmmanuel Vadot #define GCC_HMSS_DVM_BUS_CLK					81
91c66ec88fSEmmanuel Vadot #define GCC_HMSS_RBCPR_CLK					82
92c66ec88fSEmmanuel Vadot #define GCC_HMSS_TRIG_CLK					83
93c66ec88fSEmmanuel Vadot #define GCC_LPASS_AT_CLK					84
94c66ec88fSEmmanuel Vadot #define GCC_LPASS_TRIG_CLK					85
95c66ec88fSEmmanuel Vadot #define GCC_MMSS_NOC_CFG_AHB_CLK				86
96c66ec88fSEmmanuel Vadot #define GCC_MMSS_QM_AHB_CLK					87
97c66ec88fSEmmanuel Vadot #define GCC_MMSS_QM_CORE_CLK					88
98c66ec88fSEmmanuel Vadot #define GCC_MMSS_SYS_NOC_AXI_CLK				89
99c66ec88fSEmmanuel Vadot #define GCC_MSS_AT_CLK						90
100c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_AUX_CLK					91
101c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_CFG_AHB_CLK					92
102c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_MSTR_AXI_CLK					93
103c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_PIPE_CLK					94
104c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_SLV_AXI_CLK					95
105c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_AUX_CLK					96
106c66ec88fSEmmanuel Vadot #define GCC_PDM2_CLK						97
107c66ec88fSEmmanuel Vadot #define GCC_PDM_AHB_CLK						98
108c66ec88fSEmmanuel Vadot #define GCC_PDM_XO4_CLK						99
109c66ec88fSEmmanuel Vadot #define GCC_PRNG_AHB_CLK					100
110c66ec88fSEmmanuel Vadot #define GCC_SDCC2_AHB_CLK					101
111c66ec88fSEmmanuel Vadot #define GCC_SDCC2_APPS_CLK					102
112c66ec88fSEmmanuel Vadot #define GCC_SDCC4_AHB_CLK					103
113c66ec88fSEmmanuel Vadot #define GCC_SDCC4_APPS_CLK					104
114c66ec88fSEmmanuel Vadot #define GCC_TSIF_AHB_CLK					105
115c66ec88fSEmmanuel Vadot #define GCC_TSIF_INACTIVITY_TIMERS_CLK				106
116c66ec88fSEmmanuel Vadot #define GCC_TSIF_REF_CLK					107
117c66ec88fSEmmanuel Vadot #define GCC_UFS_AHB_CLK						108
118c66ec88fSEmmanuel Vadot #define GCC_UFS_AXI_CLK						109
119c66ec88fSEmmanuel Vadot #define GCC_UFS_ICE_CORE_CLK					110
120c66ec88fSEmmanuel Vadot #define GCC_UFS_PHY_AUX_CLK					111
121c66ec88fSEmmanuel Vadot #define GCC_UFS_RX_SYMBOL_0_CLK					112
122c66ec88fSEmmanuel Vadot #define GCC_UFS_RX_SYMBOL_1_CLK					113
123c66ec88fSEmmanuel Vadot #define GCC_UFS_TX_SYMBOL_0_CLK					114
124c66ec88fSEmmanuel Vadot #define GCC_UFS_UNIPRO_CORE_CLK					115
125c66ec88fSEmmanuel Vadot #define GCC_USB30_MASTER_CLK					116
126c66ec88fSEmmanuel Vadot #define GCC_USB30_MOCK_UTMI_CLK					117
127c66ec88fSEmmanuel Vadot #define GCC_USB30_SLEEP_CLK					118
128c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_AUX_CLK					119
129c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_PIPE_CLK					120
130c66ec88fSEmmanuel Vadot #define GCC_USB_PHY_CFG_AHB2PHY_CLK				121
131c66ec88fSEmmanuel Vadot #define GP1_CLK_SRC						122
132c66ec88fSEmmanuel Vadot #define GP2_CLK_SRC						123
133c66ec88fSEmmanuel Vadot #define GP3_CLK_SRC						124
134c66ec88fSEmmanuel Vadot #define GPLL0							125
135c66ec88fSEmmanuel Vadot #define GPLL0_OUT_EVEN						126
136c66ec88fSEmmanuel Vadot #define GPLL0_OUT_MAIN						127
137c66ec88fSEmmanuel Vadot #define GPLL0_OUT_ODD						128
138c66ec88fSEmmanuel Vadot #define GPLL0_OUT_TEST						129
139c66ec88fSEmmanuel Vadot #define GPLL1							130
140c66ec88fSEmmanuel Vadot #define GPLL1_OUT_EVEN						131
141c66ec88fSEmmanuel Vadot #define GPLL1_OUT_MAIN						132
142c66ec88fSEmmanuel Vadot #define GPLL1_OUT_ODD						133
143c66ec88fSEmmanuel Vadot #define GPLL1_OUT_TEST						134
144c66ec88fSEmmanuel Vadot #define GPLL2							135
145c66ec88fSEmmanuel Vadot #define GPLL2_OUT_EVEN						136
146c66ec88fSEmmanuel Vadot #define GPLL2_OUT_MAIN						137
147c66ec88fSEmmanuel Vadot #define GPLL2_OUT_ODD						138
148c66ec88fSEmmanuel Vadot #define GPLL2_OUT_TEST						139
149c66ec88fSEmmanuel Vadot #define GPLL3							140
150c66ec88fSEmmanuel Vadot #define GPLL3_OUT_EVEN						141
151c66ec88fSEmmanuel Vadot #define GPLL3_OUT_MAIN						142
152c66ec88fSEmmanuel Vadot #define GPLL3_OUT_ODD						143
153c66ec88fSEmmanuel Vadot #define GPLL3_OUT_TEST						144
154c66ec88fSEmmanuel Vadot #define GPLL4							145
155c66ec88fSEmmanuel Vadot #define GPLL4_OUT_EVEN						146
156c66ec88fSEmmanuel Vadot #define GPLL4_OUT_MAIN						147
157c66ec88fSEmmanuel Vadot #define GPLL4_OUT_ODD						148
158c66ec88fSEmmanuel Vadot #define GPLL4_OUT_TEST						149
159c66ec88fSEmmanuel Vadot #define GPLL6							150
160c66ec88fSEmmanuel Vadot #define GPLL6_OUT_EVEN						151
161c66ec88fSEmmanuel Vadot #define GPLL6_OUT_MAIN						152
162c66ec88fSEmmanuel Vadot #define GPLL6_OUT_ODD						153
163c66ec88fSEmmanuel Vadot #define GPLL6_OUT_TEST						154
164c66ec88fSEmmanuel Vadot #define HMSS_AHB_CLK_SRC					155
165c66ec88fSEmmanuel Vadot #define HMSS_RBCPR_CLK_SRC					156
166c66ec88fSEmmanuel Vadot #define PCIE_AUX_CLK_SRC					157
167c66ec88fSEmmanuel Vadot #define PDM2_CLK_SRC						158
168c66ec88fSEmmanuel Vadot #define SDCC2_APPS_CLK_SRC					159
169c66ec88fSEmmanuel Vadot #define SDCC4_APPS_CLK_SRC					160
170c66ec88fSEmmanuel Vadot #define TSIF_REF_CLK_SRC					161
171c66ec88fSEmmanuel Vadot #define UFS_AXI_CLK_SRC						162
172c66ec88fSEmmanuel Vadot #define USB30_MASTER_CLK_SRC					163
173c66ec88fSEmmanuel Vadot #define USB30_MOCK_UTMI_CLK_SRC					164
174c66ec88fSEmmanuel Vadot #define USB3_PHY_AUX_CLK_SRC					165
175c66ec88fSEmmanuel Vadot #define GCC_USB3_CLKREF_CLK					166
176c66ec88fSEmmanuel Vadot #define GCC_HDMI_CLKREF_CLK					167
177c66ec88fSEmmanuel Vadot #define GCC_UFS_CLKREF_CLK					168
178c66ec88fSEmmanuel Vadot #define GCC_PCIE_CLKREF_CLK					169
179c66ec88fSEmmanuel Vadot #define GCC_RX1_USB2_CLKREF_CLK					170
180c66ec88fSEmmanuel Vadot #define GCC_MSS_CFG_AHB_CLK					171
181c66ec88fSEmmanuel Vadot #define GCC_BOOT_ROM_AHB_CLK					172
182c66ec88fSEmmanuel Vadot #define GCC_MSS_GPLL0_DIV_CLK_SRC				173
183c66ec88fSEmmanuel Vadot #define GCC_MSS_SNOC_AXI_CLK					174
184c66ec88fSEmmanuel Vadot #define GCC_MSS_MNOC_BIMC_AXI_CLK				175
185c66ec88fSEmmanuel Vadot #define GCC_BIMC_GFX_CLK					176
186c66ec88fSEmmanuel Vadot #define UFS_UNIPRO_CORE_CLK_SRC					177
1875def4c47SEmmanuel Vadot #define GCC_MMSS_GPLL0_CLK					178
1885def4c47SEmmanuel Vadot #define HMSS_GPLL0_CLK_SRC					179
189d5b0e70fSEmmanuel Vadot #define GCC_IM_SLEEP						180
190d5b0e70fSEmmanuel Vadot #define AGGRE2_SNOC_NORTH_AXI					181
191d5b0e70fSEmmanuel Vadot #define SSC_XO							182
192d5b0e70fSEmmanuel Vadot #define SSC_CNOC_AHBS_CLK					183
193aa1a8ff2SEmmanuel Vadot #define GCC_MMSS_GPLL0_DIV_CLK					184
194aa1a8ff2SEmmanuel Vadot #define GCC_GPU_GPLL0_DIV_CLK					185
195aa1a8ff2SEmmanuel Vadot #define GCC_GPU_GPLL0_CLK					186
196*b2d2a78aSEmmanuel Vadot #define HLOS1_VOTE_LPASS_CORE_SMMU_CLK				187
197*b2d2a78aSEmmanuel Vadot #define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK				188
198*b2d2a78aSEmmanuel Vadot #define GCC_MSS_Q6_BIMC_AXI_CLK					189
199c66ec88fSEmmanuel Vadot 
200c66ec88fSEmmanuel Vadot #define PCIE_0_GDSC						0
201c66ec88fSEmmanuel Vadot #define UFS_GDSC						1
202c66ec88fSEmmanuel Vadot #define USB_30_GDSC						2
203*b2d2a78aSEmmanuel Vadot #define LPASS_ADSP_GDSC						3
204*b2d2a78aSEmmanuel Vadot #define LPASS_CORE_GDSC						4
205c66ec88fSEmmanuel Vadot 
206c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_BCR					0
207c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_BCR					1
208c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_BCR					2
209c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_BCR					3
210c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP5_BCR					4
211c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP6_BCR					5
212c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP1_BCR					6
213c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP2_BCR					7
214c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP3_BCR					8
215c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP4_BCR					9
216c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP5_BCR					10
217c66ec88fSEmmanuel Vadot #define GCC_BLSP2_QUP6_BCR					11
218c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_BCR						12
219c66ec88fSEmmanuel Vadot #define GCC_PDM_BCR						13
220c66ec88fSEmmanuel Vadot #define GCC_SDCC2_BCR						14
221c66ec88fSEmmanuel Vadot #define GCC_SDCC4_BCR						15
222c66ec88fSEmmanuel Vadot #define GCC_TSIF_BCR						16
223c66ec88fSEmmanuel Vadot #define GCC_UFS_BCR						17
224c66ec88fSEmmanuel Vadot #define GCC_USB_30_BCR						18
225c66ec88fSEmmanuel Vadot #define GCC_SYSTEM_NOC_BCR					19
226c66ec88fSEmmanuel Vadot #define GCC_CONFIG_NOC_BCR					20
227c66ec88fSEmmanuel Vadot #define GCC_AHB2PHY_EAST_BCR					21
228c66ec88fSEmmanuel Vadot #define GCC_IMEM_BCR						22
229c66ec88fSEmmanuel Vadot #define GCC_PIMEM_BCR						23
230c66ec88fSEmmanuel Vadot #define GCC_MMSS_BCR						24
231c66ec88fSEmmanuel Vadot #define GCC_QDSS_BCR						25
232c66ec88fSEmmanuel Vadot #define GCC_WCSS_BCR						26
233c66ec88fSEmmanuel Vadot #define GCC_BLSP1_BCR						27
234c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART1_BCR					28
235c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART2_BCR					29
236c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART3_BCR					30
237c66ec88fSEmmanuel Vadot #define GCC_CM_PHY_REFGEN1_BCR					31
238c66ec88fSEmmanuel Vadot #define GCC_CM_PHY_REFGEN2_BCR					32
239c66ec88fSEmmanuel Vadot #define GCC_BLSP2_BCR						33
240c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART1_BCR					34
241c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART2_BCR					35
242c66ec88fSEmmanuel Vadot #define GCC_BLSP2_UART3_BCR					36
243c66ec88fSEmmanuel Vadot #define GCC_SRAM_SENSOR_BCR					37
244c66ec88fSEmmanuel Vadot #define GCC_PRNG_BCR						38
245c66ec88fSEmmanuel Vadot #define GCC_TSIF_0_RESET					39
246c66ec88fSEmmanuel Vadot #define GCC_TSIF_1_RESET					40
247c66ec88fSEmmanuel Vadot #define GCC_TCSR_BCR						41
248c66ec88fSEmmanuel Vadot #define GCC_BOOT_ROM_BCR					42
249c66ec88fSEmmanuel Vadot #define GCC_MSG_RAM_BCR						43
250c66ec88fSEmmanuel Vadot #define GCC_TLMM_BCR						44
251c66ec88fSEmmanuel Vadot #define GCC_MPM_BCR						45
252c66ec88fSEmmanuel Vadot #define GCC_SEC_CTRL_BCR					46
253c66ec88fSEmmanuel Vadot #define GCC_SPMI_BCR						47
254c66ec88fSEmmanuel Vadot #define GCC_SPDM_BCR						48
255c66ec88fSEmmanuel Vadot #define GCC_CE1_BCR						49
256c66ec88fSEmmanuel Vadot #define GCC_BIMC_BCR						50
257c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT0_BCR				51
258c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT1_BCR				52
259c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT3_BCR				53
260c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				54
261c66ec88fSEmmanuel Vadot #define GCC_PNOC_BUS_TIMEOUT0_BCR				55
262c66ec88fSEmmanuel Vadot #define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR			56
263c66ec88fSEmmanuel Vadot #define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR			57
264c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT0_BCR				58
265c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT1_BCR				59
266c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT2_BCR				60
267c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT3_BCR				61
268c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT4_BCR				62
269c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT5_BCR				63
270c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT6_BCR				64
271c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT7_BCR				65
272c66ec88fSEmmanuel Vadot #define GCC_APB2JTAG_BCR					66
273c66ec88fSEmmanuel Vadot #define GCC_RBCPR_CX_BCR					67
274c66ec88fSEmmanuel Vadot #define GCC_RBCPR_MX_BCR					68
275c66ec88fSEmmanuel Vadot #define GCC_USB3_PHY_BCR					69
276c66ec88fSEmmanuel Vadot #define GCC_USB3PHY_PHY_BCR					70
277c66ec88fSEmmanuel Vadot #define GCC_USB3_DP_PHY_BCR					71
278c66ec88fSEmmanuel Vadot #define GCC_SSC_BCR						72
279c66ec88fSEmmanuel Vadot #define GCC_SSC_RESET						73
280c66ec88fSEmmanuel Vadot #define GCC_USB_PHY_CFG_AHB2PHY_BCR				74
281c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_LINK_DOWN_BCR				75
282c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_PHY_BCR					76
283c66ec88fSEmmanuel Vadot #define GCC_PCIE_0_NOCSR_COM_PHY_BCR				77
284c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_BCR					78
285c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR				79
286c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_CFG_AHB_BCR				80
287c66ec88fSEmmanuel Vadot #define GCC_PCIE_PHY_COM_BCR					81
288c66ec88fSEmmanuel Vadot #define GCC_GPU_BCR						82
289c66ec88fSEmmanuel Vadot #define GCC_SPSS_BCR						83
290c66ec88fSEmmanuel Vadot #define GCC_OBT_ODT_BCR						84
291c66ec88fSEmmanuel Vadot #define GCC_VS_BCR						85
292c66ec88fSEmmanuel Vadot #define GCC_MSS_VS_RESET					86
293c66ec88fSEmmanuel Vadot #define GCC_GPU_VS_RESET					87
294c66ec88fSEmmanuel Vadot #define GCC_APC0_VS_RESET					88
295c66ec88fSEmmanuel Vadot #define GCC_APC1_VS_RESET					89
296c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT8_BCR				90
297c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT9_BCR				91
298c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT10_BCR				92
299c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT11_BCR				93
300c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT12_BCR				94
301c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT13_BCR				95
302c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT14_BCR				96
303c66ec88fSEmmanuel Vadot #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				97
304c66ec88fSEmmanuel Vadot #define GCC_AGGRE1_NOC_BCR					98
305c66ec88fSEmmanuel Vadot #define GCC_AGGRE2_NOC_BCR					99
306c66ec88fSEmmanuel Vadot #define GCC_DCC_BCR						100
307c66ec88fSEmmanuel Vadot #define GCC_QREFS_VBG_CAL_BCR					101
308c66ec88fSEmmanuel Vadot #define GCC_IPA_BCR						102
309c66ec88fSEmmanuel Vadot #define GCC_GLM_BCR						103
310c66ec88fSEmmanuel Vadot #define GCC_SKL_BCR						104
311c66ec88fSEmmanuel Vadot #define GCC_MSMPU_BCR						105
312c66ec88fSEmmanuel Vadot #define GCC_QUSB2PHY_PRIM_BCR					106
313c66ec88fSEmmanuel Vadot #define GCC_QUSB2PHY_SEC_BCR					107
314c66ec88fSEmmanuel Vadot #define GCC_MSS_RESTART						108
315c66ec88fSEmmanuel Vadot 
316c66ec88fSEmmanuel Vadot #endif
317