1*833e5d42SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*833e5d42SEmmanuel Vadot /* 3*833e5d42SEmmanuel Vadot * Copyright 2025 NXP 4*833e5d42SEmmanuel Vadot */ 5*833e5d42SEmmanuel Vadot 6*833e5d42SEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_IMX94_H 7*833e5d42SEmmanuel Vadot #define __DT_BINDINGS_CLOCK_IMX94_H 8*833e5d42SEmmanuel Vadot 9*833e5d42SEmmanuel Vadot #define IMX94_CLK_DISPMIX_CLK_SEL 0 10*833e5d42SEmmanuel Vadot 11*833e5d42SEmmanuel Vadot #define IMX94_CLK_DISPMIX_LVDS_CLK_GATE 0 12*833e5d42SEmmanuel Vadot 13*833e5d42SEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_IMX94_H */ 14