1*7d0873ebSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2*7d0873ebSEmmanuel Vadot /* 3*7d0873ebSEmmanuel Vadot * Copyright 2024 NXP 4*7d0873ebSEmmanuel Vadot */ 5*7d0873ebSEmmanuel Vadot 6*7d0873ebSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_IMX95_H 7*7d0873ebSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_IMX95_H 8*7d0873ebSEmmanuel Vadot 9*7d0873ebSEmmanuel Vadot #define IMX95_CLK_VPUBLK_WAVE 0 10*7d0873ebSEmmanuel Vadot #define IMX95_CLK_VPUBLK_JPEG_ENC 1 11*7d0873ebSEmmanuel Vadot #define IMX95_CLK_VPUBLK_JPEG_DEC 2 12*7d0873ebSEmmanuel Vadot 13*7d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_CSI2_FOR0 0 14*7d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_CSI2_FOR1 1 15*7d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_ISP_AXI 2 16*7d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_ISP_PIXEL 3 17*7d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_ISP 4 18*7d0873ebSEmmanuel Vadot 19*7d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0 20*7d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1 21*7d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2 22*7d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3 23*7d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4 24*7d0873ebSEmmanuel Vadot 25*7d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_ENG0_SEL 0 26*7d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_ENG1_SEL 1 27*7d0873ebSEmmanuel Vadot 28*7d0873ebSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_IMX95_H */ 29