17d0873ebSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 27d0873ebSEmmanuel Vadot /* 37d0873ebSEmmanuel Vadot * Copyright 2024 NXP 47d0873ebSEmmanuel Vadot */ 57d0873ebSEmmanuel Vadot 67d0873ebSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_IMX95_H 77d0873ebSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_IMX95_H 87d0873ebSEmmanuel Vadot 97d0873ebSEmmanuel Vadot #define IMX95_CLK_VPUBLK_WAVE 0 107d0873ebSEmmanuel Vadot #define IMX95_CLK_VPUBLK_JPEG_ENC 1 117d0873ebSEmmanuel Vadot #define IMX95_CLK_VPUBLK_JPEG_DEC 2 127d0873ebSEmmanuel Vadot 137d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_CSI2_FOR0 0 147d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_CSI2_FOR1 1 157d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_ISP_AXI 2 167d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_ISP_PIXEL 3 177d0873ebSEmmanuel Vadot #define IMX95_CLK_CAMBLK_ISP 4 187d0873ebSEmmanuel Vadot 197d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0 207d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1 217d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2 227d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3 237d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4 247d0873ebSEmmanuel Vadot 257d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_ENG0_SEL 0 267d0873ebSEmmanuel Vadot #define IMX95_CLK_DISPMIX_ENG1_SEL 1 277d0873ebSEmmanuel Vadot 28*b2d2a78aSEmmanuel Vadot #define IMX95_CLK_NETCMIX_ENETC0_RMII 0 29*b2d2a78aSEmmanuel Vadot #define IMX95_CLK_NETCMIX_ENETC1_RMII 1 30*b2d2a78aSEmmanuel Vadot 317d0873ebSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_IMX95_H */ 32