1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Chen Zhong <chen.zhong@mediatek.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_MT7622_H 8 #define _DT_BINDINGS_CLK_MT7622_H 9 10 /* TOPCKGEN */ 11 12 #define CLK_TOP_TO_U2_PHY 0 13 #define CLK_TOP_TO_U2_PHY_1P 1 14 #define CLK_TOP_PCIE0_PIPE_EN 2 15 #define CLK_TOP_PCIE1_PIPE_EN 3 16 #define CLK_TOP_SSUSB_TX250M 4 17 #define CLK_TOP_SSUSB_EQ_RX250M 5 18 #define CLK_TOP_SSUSB_CDR_REF 6 19 #define CLK_TOP_SSUSB_CDR_FB 7 20 #define CLK_TOP_SATA_ASIC 8 21 #define CLK_TOP_SATA_RBC 9 22 #define CLK_TOP_TO_USB3_SYS 10 23 #define CLK_TOP_P1_1MHZ 11 24 #define CLK_TOP_4MHZ 12 25 #define CLK_TOP_P0_1MHZ 13 26 #define CLK_TOP_TXCLK_SRC_PRE 14 27 #define CLK_TOP_RTC 15 28 #define CLK_TOP_MEMPLL 16 29 #define CLK_TOP_DMPLL 17 30 #define CLK_TOP_SYSPLL_D2 18 31 #define CLK_TOP_SYSPLL1_D2 19 32 #define CLK_TOP_SYSPLL1_D4 20 33 #define CLK_TOP_SYSPLL1_D8 21 34 #define CLK_TOP_SYSPLL2_D4 22 35 #define CLK_TOP_SYSPLL2_D8 23 36 #define CLK_TOP_SYSPLL_D5 24 37 #define CLK_TOP_SYSPLL3_D2 25 38 #define CLK_TOP_SYSPLL3_D4 26 39 #define CLK_TOP_SYSPLL4_D2 27 40 #define CLK_TOP_SYSPLL4_D4 28 41 #define CLK_TOP_SYSPLL4_D16 29 42 #define CLK_TOP_UNIVPLL 30 43 #define CLK_TOP_UNIVPLL_D2 31 44 #define CLK_TOP_UNIVPLL1_D2 32 45 #define CLK_TOP_UNIVPLL1_D4 33 46 #define CLK_TOP_UNIVPLL1_D8 34 47 #define CLK_TOP_UNIVPLL1_D16 35 48 #define CLK_TOP_UNIVPLL2_D2 36 49 #define CLK_TOP_UNIVPLL2_D4 37 50 #define CLK_TOP_UNIVPLL2_D8 38 51 #define CLK_TOP_UNIVPLL2_D16 39 52 #define CLK_TOP_UNIVPLL_D5 40 53 #define CLK_TOP_UNIVPLL3_D2 41 54 #define CLK_TOP_UNIVPLL3_D4 42 55 #define CLK_TOP_UNIVPLL3_D16 43 56 #define CLK_TOP_UNIVPLL_D7 44 57 #define CLK_TOP_UNIVPLL_D80_D4 45 58 #define CLK_TOP_UNIV48M 46 59 #define CLK_TOP_SGMIIPLL 47 60 #define CLK_TOP_SGMIIPLL_D2 48 61 #define CLK_TOP_AUD1PLL 49 62 #define CLK_TOP_AUD2PLL 50 63 #define CLK_TOP_AUD_I2S2_MCK 51 64 #define CLK_TOP_TO_USB3_REF 52 65 #define CLK_TOP_PCIE1_MAC_EN 53 66 #define CLK_TOP_PCIE0_MAC_EN 54 67 #define CLK_TOP_ETH_500M 55 68 #define CLK_TOP_AXI_SEL 56 69 #define CLK_TOP_MEM_SEL 57 70 #define CLK_TOP_DDRPHYCFG_SEL 58 71 #define CLK_TOP_ETH_SEL 59 72 #define CLK_TOP_PWM_SEL 60 73 #define CLK_TOP_F10M_REF_SEL 61 74 #define CLK_TOP_NFI_INFRA_SEL 62 75 #define CLK_TOP_FLASH_SEL 63 76 #define CLK_TOP_UART_SEL 64 77 #define CLK_TOP_SPI0_SEL 65 78 #define CLK_TOP_SPI1_SEL 66 79 #define CLK_TOP_MSDC50_0_SEL 67 80 #define CLK_TOP_MSDC30_0_SEL 68 81 #define CLK_TOP_MSDC30_1_SEL 69 82 #define CLK_TOP_A1SYS_HP_SEL 70 83 #define CLK_TOP_A2SYS_HP_SEL 71 84 #define CLK_TOP_INTDIR_SEL 72 85 #define CLK_TOP_AUD_INTBUS_SEL 73 86 #define CLK_TOP_PMICSPI_SEL 74 87 #define CLK_TOP_SCP_SEL 75 88 #define CLK_TOP_ATB_SEL 76 89 #define CLK_TOP_HIF_SEL 77 90 #define CLK_TOP_AUDIO_SEL 78 91 #define CLK_TOP_U2_SEL 79 92 #define CLK_TOP_AUD1_SEL 80 93 #define CLK_TOP_AUD2_SEL 81 94 #define CLK_TOP_IRRX_SEL 82 95 #define CLK_TOP_IRTX_SEL 83 96 #define CLK_TOP_ASM_L_SEL 84 97 #define CLK_TOP_ASM_M_SEL 85 98 #define CLK_TOP_ASM_H_SEL 86 99 #define CLK_TOP_APLL1_SEL 87 100 #define CLK_TOP_APLL2_SEL 88 101 #define CLK_TOP_I2S0_MCK_SEL 89 102 #define CLK_TOP_I2S1_MCK_SEL 90 103 #define CLK_TOP_I2S2_MCK_SEL 91 104 #define CLK_TOP_I2S3_MCK_SEL 92 105 #define CLK_TOP_APLL1_DIV 93 106 #define CLK_TOP_APLL2_DIV 94 107 #define CLK_TOP_I2S0_MCK_DIV 95 108 #define CLK_TOP_I2S1_MCK_DIV 96 109 #define CLK_TOP_I2S2_MCK_DIV 97 110 #define CLK_TOP_I2S3_MCK_DIV 98 111 #define CLK_TOP_A1SYS_HP_DIV 99 112 #define CLK_TOP_A2SYS_HP_DIV 100 113 #define CLK_TOP_APLL1_DIV_PD 101 114 #define CLK_TOP_APLL2_DIV_PD 102 115 #define CLK_TOP_I2S0_MCK_DIV_PD 103 116 #define CLK_TOP_I2S1_MCK_DIV_PD 104 117 #define CLK_TOP_I2S2_MCK_DIV_PD 105 118 #define CLK_TOP_I2S3_MCK_DIV_PD 106 119 #define CLK_TOP_A1SYS_HP_DIV_PD 107 120 #define CLK_TOP_A2SYS_HP_DIV_PD 108 121 #define CLK_TOP_NR_CLK 109 122 123 /* INFRACFG */ 124 125 #define CLK_INFRA_MUX1_SEL 0 126 #define CLK_INFRA_DBGCLK_PD 1 127 #define CLK_INFRA_AUDIO_PD 2 128 #define CLK_INFRA_IRRX_PD 3 129 #define CLK_INFRA_APXGPT_PD 4 130 #define CLK_INFRA_PMIC_PD 5 131 #define CLK_INFRA_TRNG 6 132 #define CLK_INFRA_NR_CLK 7 133 134 /* PERICFG */ 135 136 #define CLK_PERIBUS_SEL 0 137 #define CLK_PERI_THERM_PD 1 138 #define CLK_PERI_PWM1_PD 2 139 #define CLK_PERI_PWM2_PD 3 140 #define CLK_PERI_PWM3_PD 4 141 #define CLK_PERI_PWM4_PD 5 142 #define CLK_PERI_PWM5_PD 6 143 #define CLK_PERI_PWM6_PD 7 144 #define CLK_PERI_PWM7_PD 8 145 #define CLK_PERI_PWM_PD 9 146 #define CLK_PERI_AP_DMA_PD 10 147 #define CLK_PERI_MSDC30_0_PD 11 148 #define CLK_PERI_MSDC30_1_PD 12 149 #define CLK_PERI_UART0_PD 13 150 #define CLK_PERI_UART1_PD 14 151 #define CLK_PERI_UART2_PD 15 152 #define CLK_PERI_UART3_PD 16 153 #define CLK_PERI_UART4_PD 17 154 #define CLK_PERI_BTIF_PD 18 155 #define CLK_PERI_I2C0_PD 19 156 #define CLK_PERI_I2C1_PD 20 157 #define CLK_PERI_I2C2_PD 21 158 #define CLK_PERI_SPI1_PD 22 159 #define CLK_PERI_AUXADC_PD 23 160 #define CLK_PERI_SPI0_PD 24 161 #define CLK_PERI_SNFI_PD 25 162 #define CLK_PERI_NFI_PD 26 163 #define CLK_PERI_NFIECC_PD 27 164 #define CLK_PERI_FLASH_PD 28 165 #define CLK_PERI_IRTX_PD 29 166 #define CLK_PERI_NR_CLK 30 167 168 /* APMIXEDSYS */ 169 170 #define CLK_APMIXED_ARMPLL 0 171 #define CLK_APMIXED_MAINPLL 1 172 #define CLK_APMIXED_UNIV2PLL 2 173 #define CLK_APMIXED_ETH1PLL 3 174 #define CLK_APMIXED_ETH2PLL 4 175 #define CLK_APMIXED_AUD1PLL 5 176 #define CLK_APMIXED_AUD2PLL 6 177 #define CLK_APMIXED_TRGPLL 7 178 #define CLK_APMIXED_SGMIPLL 8 179 #define CLK_APMIXED_MAIN_CORE_EN 9 180 #define CLK_APMIXED_NR_CLK 10 181 182 /* AUDIOSYS */ 183 184 #define CLK_AUDIO_AFE 0 185 #define CLK_AUDIO_HDMI 1 186 #define CLK_AUDIO_SPDF 2 187 #define CLK_AUDIO_APLL 3 188 #define CLK_AUDIO_I2SIN1 4 189 #define CLK_AUDIO_I2SIN2 5 190 #define CLK_AUDIO_I2SIN3 6 191 #define CLK_AUDIO_I2SIN4 7 192 #define CLK_AUDIO_I2SO1 8 193 #define CLK_AUDIO_I2SO2 9 194 #define CLK_AUDIO_I2SO3 10 195 #define CLK_AUDIO_I2SO4 11 196 #define CLK_AUDIO_ASRCI1 12 197 #define CLK_AUDIO_ASRCI2 13 198 #define CLK_AUDIO_ASRCO1 14 199 #define CLK_AUDIO_ASRCO2 15 200 #define CLK_AUDIO_INTDIR 16 201 #define CLK_AUDIO_A1SYS 17 202 #define CLK_AUDIO_A2SYS 18 203 #define CLK_AUDIO_UL1 19 204 #define CLK_AUDIO_UL2 20 205 #define CLK_AUDIO_UL3 21 206 #define CLK_AUDIO_UL4 22 207 #define CLK_AUDIO_UL5 23 208 #define CLK_AUDIO_UL6 24 209 #define CLK_AUDIO_DL1 25 210 #define CLK_AUDIO_DL2 26 211 #define CLK_AUDIO_DL3 27 212 #define CLK_AUDIO_DL4 28 213 #define CLK_AUDIO_DL5 29 214 #define CLK_AUDIO_DL6 30 215 #define CLK_AUDIO_DLMCH 31 216 #define CLK_AUDIO_ARB1 32 217 #define CLK_AUDIO_AWB 33 218 #define CLK_AUDIO_AWB2 34 219 #define CLK_AUDIO_DAI 35 220 #define CLK_AUDIO_MOD 36 221 #define CLK_AUDIO_ASRCI3 37 222 #define CLK_AUDIO_ASRCI4 38 223 #define CLK_AUDIO_ASRCO3 39 224 #define CLK_AUDIO_ASRCO4 40 225 #define CLK_AUDIO_MEM_ASRC1 41 226 #define CLK_AUDIO_MEM_ASRC2 42 227 #define CLK_AUDIO_MEM_ASRC3 43 228 #define CLK_AUDIO_MEM_ASRC4 44 229 #define CLK_AUDIO_MEM_ASRC5 45 230 #define CLK_AUDIO_AFE_CONN 46 231 #define CLK_AUDIO_NR_CLK 47 232 233 /* SSUSBSYS */ 234 235 #define CLK_SSUSB_U2_PHY_1P_EN 0 236 #define CLK_SSUSB_U2_PHY_EN 1 237 #define CLK_SSUSB_REF_EN 2 238 #define CLK_SSUSB_SYS_EN 3 239 #define CLK_SSUSB_MCU_EN 4 240 #define CLK_SSUSB_DMA_EN 5 241 #define CLK_SSUSB_NR_CLK 6 242 243 /* PCIESYS */ 244 245 #define CLK_PCIE_P1_AUX_EN 0 246 #define CLK_PCIE_P1_OBFF_EN 1 247 #define CLK_PCIE_P1_AHB_EN 2 248 #define CLK_PCIE_P1_AXI_EN 3 249 #define CLK_PCIE_P1_MAC_EN 4 250 #define CLK_PCIE_P1_PIPE_EN 5 251 #define CLK_PCIE_P0_AUX_EN 6 252 #define CLK_PCIE_P0_OBFF_EN 7 253 #define CLK_PCIE_P0_AHB_EN 8 254 #define CLK_PCIE_P0_AXI_EN 9 255 #define CLK_PCIE_P0_MAC_EN 10 256 #define CLK_PCIE_P0_PIPE_EN 11 257 #define CLK_SATA_AHB_EN 12 258 #define CLK_SATA_AXI_EN 13 259 #define CLK_SATA_ASIC_EN 14 260 #define CLK_SATA_RBC_EN 15 261 #define CLK_SATA_PM_EN 16 262 #define CLK_PCIE_NR_CLK 17 263 264 /* ETHSYS */ 265 266 #define CLK_ETH_HSDMA_EN 0 267 #define CLK_ETH_ESW_EN 1 268 #define CLK_ETH_GP2_EN 2 269 #define CLK_ETH_GP1_EN 3 270 #define CLK_ETH_GP0_EN 4 271 #define CLK_ETH_NR_CLK 5 272 273 /* SGMIISYS */ 274 275 #define CLK_SGMII_TX250M_EN 0 276 #define CLK_SGMII_RX250M_EN 1 277 #define CLK_SGMII_CDR_REF 2 278 #define CLK_SGMII_CDR_FB 3 279 #define CLK_SGMII_NR_CLK 4 280 281 #endif /* _DT_BINDINGS_CLK_MT7622_H */ 282 283