1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (c) 2019 Microchip Inc. 4*c66ec88fSEmmanuel Vadot * 5*c66ec88fSEmmanuel Vadot * Author: Lars Povlsen <lars.povlsen@microchip.com> 6*c66ec88fSEmmanuel Vadot */ 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_SPARX5_H 9*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLK_SPARX5_H 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel Vadot #define CLK_ID_CORE 0 12*c66ec88fSEmmanuel Vadot #define CLK_ID_DDR 1 13*c66ec88fSEmmanuel Vadot #define CLK_ID_CPU2 2 14*c66ec88fSEmmanuel Vadot #define CLK_ID_ARM2 3 15*c66ec88fSEmmanuel Vadot #define CLK_ID_AUX1 4 16*c66ec88fSEmmanuel Vadot #define CLK_ID_AUX2 5 17*c66ec88fSEmmanuel Vadot #define CLK_ID_AUX3 6 18*c66ec88fSEmmanuel Vadot #define CLK_ID_AUX4 7 19*c66ec88fSEmmanuel Vadot #define CLK_ID_SYNCE 8 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel Vadot #define N_CLOCKS 9 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel Vadot #endif 24