xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/mediatek,mt6735-infracfg.h (revision 5f62a964e9f8abc6a05d8338273fadd154f0a206)
1*5f62a964SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*5f62a964SEmmanuel Vadot 
3*5f62a964SEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H
4*5f62a964SEmmanuel Vadot #define _DT_BINDINGS_CLK_MT6735_INFRACFG_H
5*5f62a964SEmmanuel Vadot 
6*5f62a964SEmmanuel Vadot #define CLK_INFRA_DBG			0
7*5f62a964SEmmanuel Vadot #define CLK_INFRA_GCE			1
8*5f62a964SEmmanuel Vadot #define CLK_INFRA_TRBG			2
9*5f62a964SEmmanuel Vadot #define CLK_INFRA_CPUM			3
10*5f62a964SEmmanuel Vadot #define CLK_INFRA_DEVAPC		4
11*5f62a964SEmmanuel Vadot #define CLK_INFRA_AUDIO			5
12*5f62a964SEmmanuel Vadot #define CLK_INFRA_GCPU			6
13*5f62a964SEmmanuel Vadot #define CLK_INFRA_L2C_SRAM		7
14*5f62a964SEmmanuel Vadot #define CLK_INFRA_M4U			8
15*5f62a964SEmmanuel Vadot #define CLK_INFRA_CLDMA			9
16*5f62a964SEmmanuel Vadot #define CLK_INFRA_CONNMCU_BUS		10
17*5f62a964SEmmanuel Vadot #define CLK_INFRA_KP			11
18*5f62a964SEmmanuel Vadot #define CLK_INFRA_APXGPT		12
19*5f62a964SEmmanuel Vadot #define CLK_INFRA_SEJ			13
20*5f62a964SEmmanuel Vadot #define CLK_INFRA_CCIF0_AP		14
21*5f62a964SEmmanuel Vadot #define CLK_INFRA_CCIF1_AP		15
22*5f62a964SEmmanuel Vadot #define CLK_INFRA_PMIC_SPI		16
23*5f62a964SEmmanuel Vadot #define CLK_INFRA_PMIC_WRAP		17
24*5f62a964SEmmanuel Vadot 
25*5f62a964SEmmanuel Vadot #endif
26