1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (c) 2014 LSI Corporation 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_AXM5516_H 7*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLK_AXM5516_H 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_FAB_PLL 0 10*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_CPU_PLL 1 11*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_SYS_PLL 2 12*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_SM0_PLL 3 13*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_SM1_PLL 4 14*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_FAB_DIV 5 15*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_SYS_DIV 6 16*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_NRCP_DIV 7 17*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_CPU0_DIV 8 18*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_CPU1_DIV 9 19*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_CPU2_DIV 10 20*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_CPU3_DIV 11 21*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_PER_DIV 12 22*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_MMC_DIV 13 23*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_FAB 14 24*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_SYS 15 25*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_NRCP 16 26*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_CPU0 17 27*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_CPU1 18 28*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_CPU2 19 29*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_CPU3 20 30*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_PER 21 31*c66ec88fSEmmanuel Vadot #define AXXIA_CLK_MMC 22 32*c66ec88fSEmmanuel Vadot 33*c66ec88fSEmmanuel Vadot #endif 34