1*8cc087a1SEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*8cc087a1SEmmanuel Vadot /* 3*8cc087a1SEmmanuel Vadot * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. 4*8cc087a1SEmmanuel Vadot */ 5*8cc087a1SEmmanuel Vadot 6*8cc087a1SEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ 7*8cc087a1SEmmanuel Vadot #define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ 8*8cc087a1SEmmanuel Vadot 9*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_EXT 0 10*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_OSC32K 1 11*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_PLL 2 12*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_PLL_HALF 3 13*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_CCLK 4 14*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_HCLK 5 15*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_PCLK 6 16*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_MCLK 7 17*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_IPU 8 18*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_LCD 9 19*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_I2S 10 20*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_SPI 11 21*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_MMC_MUX 12 22*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_UDC 13 23*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_UART 14 24*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_DMA 15 25*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_ADC 16 26*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_I2C 17 27*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_AIC 18 28*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_MMC0 19 29*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_MMC1 20 30*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_BCH 21 31*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_TCU 22 32*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_EXT512 23 33*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_RTC 24 34*8cc087a1SEmmanuel Vadot #define JZ4725B_CLK_UDC_PHY 25 35*8cc087a1SEmmanuel Vadot 36*8cc087a1SEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ 37