1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 4*c66ec88fSEmmanuel Vadot * 5*c66ec88fSEmmanuel Vadot * Baikal-T1 CCU clock indices 6*c66ec88fSEmmanuel Vadot */ 7*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H 8*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_BT1_CCU_H 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel Vadot #define CCU_CPU_PLL 0 11*c66ec88fSEmmanuel Vadot #define CCU_SATA_PLL 1 12*c66ec88fSEmmanuel Vadot #define CCU_DDR_PLL 2 13*c66ec88fSEmmanuel Vadot #define CCU_PCIE_PLL 3 14*c66ec88fSEmmanuel Vadot #define CCU_ETH_PLL 4 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel Vadot #define CCU_AXI_MAIN_CLK 0 17*c66ec88fSEmmanuel Vadot #define CCU_AXI_DDR_CLK 1 18*c66ec88fSEmmanuel Vadot #define CCU_AXI_SATA_CLK 2 19*c66ec88fSEmmanuel Vadot #define CCU_AXI_GMAC0_CLK 3 20*c66ec88fSEmmanuel Vadot #define CCU_AXI_GMAC1_CLK 4 21*c66ec88fSEmmanuel Vadot #define CCU_AXI_XGMAC_CLK 5 22*c66ec88fSEmmanuel Vadot #define CCU_AXI_PCIE_M_CLK 6 23*c66ec88fSEmmanuel Vadot #define CCU_AXI_PCIE_S_CLK 7 24*c66ec88fSEmmanuel Vadot #define CCU_AXI_USB_CLK 8 25*c66ec88fSEmmanuel Vadot #define CCU_AXI_HWA_CLK 9 26*c66ec88fSEmmanuel Vadot #define CCU_AXI_SRAM_CLK 10 27*c66ec88fSEmmanuel Vadot 28*c66ec88fSEmmanuel Vadot #define CCU_SYS_SATA_REF_CLK 0 29*c66ec88fSEmmanuel Vadot #define CCU_SYS_APB_CLK 1 30*c66ec88fSEmmanuel Vadot #define CCU_SYS_GMAC0_TX_CLK 2 31*c66ec88fSEmmanuel Vadot #define CCU_SYS_GMAC0_PTP_CLK 3 32*c66ec88fSEmmanuel Vadot #define CCU_SYS_GMAC1_TX_CLK 4 33*c66ec88fSEmmanuel Vadot #define CCU_SYS_GMAC1_PTP_CLK 5 34*c66ec88fSEmmanuel Vadot #define CCU_SYS_XGMAC_REF_CLK 6 35*c66ec88fSEmmanuel Vadot #define CCU_SYS_XGMAC_PTP_CLK 7 36*c66ec88fSEmmanuel Vadot #define CCU_SYS_USB_CLK 8 37*c66ec88fSEmmanuel Vadot #define CCU_SYS_PVT_CLK 9 38*c66ec88fSEmmanuel Vadot #define CCU_SYS_HWA_CLK 10 39*c66ec88fSEmmanuel Vadot #define CCU_SYS_UART_CLK 11 40*c66ec88fSEmmanuel Vadot #define CCU_SYS_I2C1_CLK 12 41*c66ec88fSEmmanuel Vadot #define CCU_SYS_I2C2_CLK 13 42*c66ec88fSEmmanuel Vadot #define CCU_SYS_GPIO_CLK 14 43*c66ec88fSEmmanuel Vadot #define CCU_SYS_TIMER0_CLK 15 44*c66ec88fSEmmanuel Vadot #define CCU_SYS_TIMER1_CLK 16 45*c66ec88fSEmmanuel Vadot #define CCU_SYS_TIMER2_CLK 17 46*c66ec88fSEmmanuel Vadot #define CCU_SYS_WDT_CLK 18 47*c66ec88fSEmmanuel Vadot 48*c66ec88fSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */ 49