1c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2c66ec88fSEmmanuel Vadot /* 3c66ec88fSEmmanuel Vadot * ARTPEC-6 clock controller indexes 4c66ec88fSEmmanuel Vadot * 5*c9ccf3a3SEmmanuel Vadot * Copyright 2016 Axis Communications AB. 6c66ec88fSEmmanuel Vadot */ 7c66ec88fSEmmanuel Vadot 8c66ec88fSEmmanuel Vadot #ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H 9c66ec88fSEmmanuel Vadot #define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H 10c66ec88fSEmmanuel Vadot 11c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_CPU 0 12c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_CPU_PERIPH 1 13c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_NAND_CLKA 2 14c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_NAND_CLKB 3 15c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_ETH_ACLK 4 16c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_DMA_ACLK 5 17c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_PTP_REF 6 18c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_SD_PCLK 7 19c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_SD_IMCLK 8 20c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_I2S_HST 9 21c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_I2S0_CLK 10 22c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_I2S1_CLK 11 23c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_UART_PCLK 12 24c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_UART_REFCLK 13 25c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_I2C 14 26c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_SPI_PCLK 15 27c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_SPI_SSPCLK 16 28c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_SYS_TIMER 17 29c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_FRACDIV_IN 18 30c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_DBG_PCLK 19 31c66ec88fSEmmanuel Vadot 32c66ec88fSEmmanuel Vadot /* This must be the highest clock index plus one. */ 33c66ec88fSEmmanuel Vadot #define ARTPEC6_CLK_NUMCLOCKS 20 34c66ec88fSEmmanuel Vadot 35c66ec88fSEmmanuel Vadot #endif 36