xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/at91.h (revision 2846c90520eb4cc74e24d586a0ea0f4a0006bc73)
1c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-or-later */
2c66ec88fSEmmanuel Vadot /*
3c66ec88fSEmmanuel Vadot  * This header provides constants for AT91 pmc status.
4c66ec88fSEmmanuel Vadot  *
5c66ec88fSEmmanuel Vadot  * The constants defined in this header are being used in dts.
6c66ec88fSEmmanuel Vadot  */
7c66ec88fSEmmanuel Vadot 
8c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLK_AT91_H
9c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLK_AT91_H
10c66ec88fSEmmanuel Vadot 
11c66ec88fSEmmanuel Vadot #define PMC_TYPE_CORE		0
12c66ec88fSEmmanuel Vadot #define PMC_TYPE_SYSTEM		1
13c66ec88fSEmmanuel Vadot #define PMC_TYPE_PERIPHERAL	2
14c66ec88fSEmmanuel Vadot #define PMC_TYPE_GCK		3
15c66ec88fSEmmanuel Vadot #define PMC_TYPE_PROGRAMMABLE	4
16c66ec88fSEmmanuel Vadot 
17c66ec88fSEmmanuel Vadot #define PMC_SLOW		0
18c66ec88fSEmmanuel Vadot #define PMC_MCK			1
19c66ec88fSEmmanuel Vadot #define PMC_UTMI		2
20c66ec88fSEmmanuel Vadot #define PMC_MAIN		3
21c66ec88fSEmmanuel Vadot #define PMC_MCK2		4
22c66ec88fSEmmanuel Vadot #define PMC_I2S0_MUX		5
23c66ec88fSEmmanuel Vadot #define PMC_I2S1_MUX		6
24c66ec88fSEmmanuel Vadot #define PMC_PLLACK		7
25c66ec88fSEmmanuel Vadot #define PMC_PLLBCK		8
26c66ec88fSEmmanuel Vadot #define PMC_AUDIOPLLCK		9
27c9ccf3a3SEmmanuel Vadot #define PMC_AUDIOPINCK		10
28c66ec88fSEmmanuel Vadot 
295def4c47SEmmanuel Vadot /* SAMA7G5 */
305def4c47SEmmanuel Vadot #define PMC_CPUPLL		(PMC_MAIN + 1)
315def4c47SEmmanuel Vadot #define PMC_SYSPLL		(PMC_MAIN + 2)
325def4c47SEmmanuel Vadot #define PMC_DDRPLL		(PMC_MAIN + 3)
335def4c47SEmmanuel Vadot #define PMC_IMGPLL		(PMC_MAIN + 4)
345def4c47SEmmanuel Vadot #define PMC_BAUDPLL		(PMC_MAIN + 5)
355def4c47SEmmanuel Vadot #define PMC_AUDIOPMCPLL		(PMC_MAIN + 6)
365def4c47SEmmanuel Vadot #define PMC_AUDIOIOPLL		(PMC_MAIN + 7)
375def4c47SEmmanuel Vadot #define PMC_ETHPLL		(PMC_MAIN + 8)
385def4c47SEmmanuel Vadot #define PMC_CPU			(PMC_MAIN + 9)
39c9ccf3a3SEmmanuel Vadot #define PMC_MCK1		(PMC_MAIN + 10)
405def4c47SEmmanuel Vadot 
41b2d2a78aSEmmanuel Vadot /* SAM9X7 */
42b2d2a78aSEmmanuel Vadot #define PMC_PLLADIV2		(PMC_MAIN + 11)
43b2d2a78aSEmmanuel Vadot #define PMC_LVDSPLL		(PMC_MAIN + 12)
44b2d2a78aSEmmanuel Vadot 
45*2846c905SEmmanuel Vadot /* SAMA7D65 */
46*2846c905SEmmanuel Vadot #define PMC_MCK3		(PMC_MAIN + 13)
47*2846c905SEmmanuel Vadot #define PMC_MCK5		(PMC_MAIN + 14)
48*2846c905SEmmanuel Vadot 
49c66ec88fSEmmanuel Vadot #ifndef AT91_PMC_MOSCS
50c66ec88fSEmmanuel Vadot #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
51c66ec88fSEmmanuel Vadot #define AT91_PMC_LOCKA		1		/* PLLA Lock */
52c66ec88fSEmmanuel Vadot #define AT91_PMC_LOCKB		2		/* PLLB Lock */
53c66ec88fSEmmanuel Vadot #define AT91_PMC_MCKRDY		3		/* Master Clock */
54c66ec88fSEmmanuel Vadot #define AT91_PMC_LOCKU		6		/* UPLL Lock */
55c66ec88fSEmmanuel Vadot #define AT91_PMC_PCKRDY(id)	(8 + (id))	/* Programmable Clock */
56c66ec88fSEmmanuel Vadot #define AT91_PMC_MOSCSELS	16		/* Main Oscillator Selection */
57c66ec88fSEmmanuel Vadot #define AT91_PMC_MOSCRCS	17		/* Main On-Chip RC */
58c66ec88fSEmmanuel Vadot #define AT91_PMC_CFDEV		18		/* Clock Failure Detector Event */
59c66ec88fSEmmanuel Vadot #define AT91_PMC_GCKRDY		24		/* Generated Clocks */
60c66ec88fSEmmanuel Vadot #endif
61c66ec88fSEmmanuel Vadot 
62*2846c905SEmmanuel Vadot /* Slow clock. */
63*2846c905SEmmanuel Vadot #define SCKC_MD_SLCK		0
64*2846c905SEmmanuel Vadot #define SCKC_TD_SLCK		1
65*2846c905SEmmanuel Vadot 
66c66ec88fSEmmanuel Vadot #endif
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