xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h (revision 84943d6f38e936ac3b7a3947ca26eeb27a39f938)
1*84943d6fSEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2*84943d6fSEmmanuel Vadot /*
3*84943d6fSEmmanuel Vadot  * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.
4*84943d6fSEmmanuel Vadot  * Author: Yu Tu <yu.tu@amlogic.com>
5*84943d6fSEmmanuel Vadot  */
6*84943d6fSEmmanuel Vadot 
7*84943d6fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
8*84943d6fSEmmanuel Vadot #define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
9*84943d6fSEmmanuel Vadot 
10*84943d6fSEmmanuel Vadot #define CLKID_RTC_32K_CLKIN		0
11*84943d6fSEmmanuel Vadot #define CLKID_RTC_32K_DIV		1
12*84943d6fSEmmanuel Vadot #define CLKID_RTC_32K_SEL		2
13*84943d6fSEmmanuel Vadot #define CLKID_RTC_32K_XATL		3
14*84943d6fSEmmanuel Vadot #define CLKID_RTC			4
15*84943d6fSEmmanuel Vadot #define CLKID_SYS_CLK_B_SEL		5
16*84943d6fSEmmanuel Vadot #define CLKID_SYS_CLK_B_DIV		6
17*84943d6fSEmmanuel Vadot #define CLKID_SYS_CLK_B			7
18*84943d6fSEmmanuel Vadot #define CLKID_SYS_CLK_A_SEL		8
19*84943d6fSEmmanuel Vadot #define CLKID_SYS_CLK_A_DIV		9
20*84943d6fSEmmanuel Vadot #define CLKID_SYS_CLK_A			10
21*84943d6fSEmmanuel Vadot #define CLKID_SYS			11
22*84943d6fSEmmanuel Vadot #define CLKID_CECA_32K_CLKIN		12
23*84943d6fSEmmanuel Vadot #define CLKID_CECA_32K_DIV		13
24*84943d6fSEmmanuel Vadot #define CLKID_CECA_32K_SEL_PRE		14
25*84943d6fSEmmanuel Vadot #define CLKID_CECA_32K_SEL		15
26*84943d6fSEmmanuel Vadot #define CLKID_CECA_32K_CLKOUT		16
27*84943d6fSEmmanuel Vadot #define CLKID_CECB_32K_CLKIN		17
28*84943d6fSEmmanuel Vadot #define CLKID_CECB_32K_DIV		18
29*84943d6fSEmmanuel Vadot #define CLKID_CECB_32K_SEL_PRE		19
30*84943d6fSEmmanuel Vadot #define CLKID_CECB_32K_SEL		20
31*84943d6fSEmmanuel Vadot #define CLKID_CECB_32K_CLKOUT		21
32*84943d6fSEmmanuel Vadot #define CLKID_SC_CLK_SEL		22
33*84943d6fSEmmanuel Vadot #define CLKID_SC_CLK_DIV		23
34*84943d6fSEmmanuel Vadot #define CLKID_SC			24
35*84943d6fSEmmanuel Vadot #define CLKID_12_24M			25
36*84943d6fSEmmanuel Vadot #define CLKID_12M_CLK_DIV		26
37*84943d6fSEmmanuel Vadot #define CLKID_12_24M_CLK_SEL		27
38*84943d6fSEmmanuel Vadot #define CLKID_VID_PLL_DIV		28
39*84943d6fSEmmanuel Vadot #define CLKID_VID_PLL_SEL		29
40*84943d6fSEmmanuel Vadot #define CLKID_VID_PLL			30
41*84943d6fSEmmanuel Vadot #define CLKID_VCLK_SEL			31
42*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_SEL			32
43*84943d6fSEmmanuel Vadot #define CLKID_VCLK_INPUT		33
44*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_INPUT		34
45*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV			35
46*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV			36
47*84943d6fSEmmanuel Vadot #define CLKID_VCLK			37
48*84943d6fSEmmanuel Vadot #define CLKID_VCLK2			38
49*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV1			39
50*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV2_EN		40
51*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV4_EN		41
52*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV6_EN		42
53*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV12_EN		43
54*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV1		44
55*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV2_EN		45
56*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV4_EN		46
57*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV6_EN		47
58*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV12_EN		48
59*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV2			49
60*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV4			50
61*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV6			51
62*84943d6fSEmmanuel Vadot #define CLKID_VCLK_DIV12		52
63*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV2		53
64*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV4		54
65*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV6		55
66*84943d6fSEmmanuel Vadot #define CLKID_VCLK2_DIV12		56
67*84943d6fSEmmanuel Vadot #define CLKID_CTS_ENCI_SEL		57
68*84943d6fSEmmanuel Vadot #define CLKID_CTS_ENCP_SEL		58
69*84943d6fSEmmanuel Vadot #define CLKID_CTS_VDAC_SEL		59
70*84943d6fSEmmanuel Vadot #define CLKID_HDMI_TX_SEL		60
71*84943d6fSEmmanuel Vadot #define CLKID_CTS_ENCI			61
72*84943d6fSEmmanuel Vadot #define CLKID_CTS_ENCP			62
73*84943d6fSEmmanuel Vadot #define CLKID_CTS_VDAC			63
74*84943d6fSEmmanuel Vadot #define CLKID_HDMI_TX			64
75*84943d6fSEmmanuel Vadot #define CLKID_HDMI_SEL			65
76*84943d6fSEmmanuel Vadot #define CLKID_HDMI_DIV			66
77*84943d6fSEmmanuel Vadot #define CLKID_HDMI			67
78*84943d6fSEmmanuel Vadot #define CLKID_TS_CLK_DIV		68
79*84943d6fSEmmanuel Vadot #define CLKID_TS			69
80*84943d6fSEmmanuel Vadot #define CLKID_MALI_0_SEL		70
81*84943d6fSEmmanuel Vadot #define CLKID_MALI_0_DIV		71
82*84943d6fSEmmanuel Vadot #define CLKID_MALI_0			72
83*84943d6fSEmmanuel Vadot #define CLKID_MALI_1_SEL		73
84*84943d6fSEmmanuel Vadot #define CLKID_MALI_1_DIV		74
85*84943d6fSEmmanuel Vadot #define CLKID_MALI_1			75
86*84943d6fSEmmanuel Vadot #define CLKID_MALI_SEL			76
87*84943d6fSEmmanuel Vadot #define CLKID_VDEC_P0_SEL		77
88*84943d6fSEmmanuel Vadot #define CLKID_VDEC_P0_DIV		78
89*84943d6fSEmmanuel Vadot #define CLKID_VDEC_P0			79
90*84943d6fSEmmanuel Vadot #define CLKID_VDEC_P1_SEL		80
91*84943d6fSEmmanuel Vadot #define CLKID_VDEC_P1_DIV		81
92*84943d6fSEmmanuel Vadot #define CLKID_VDEC_P1			82
93*84943d6fSEmmanuel Vadot #define CLKID_VDEC_SEL			83
94*84943d6fSEmmanuel Vadot #define CLKID_HEVCF_P0_SEL		84
95*84943d6fSEmmanuel Vadot #define CLKID_HEVCF_P0_DIV		85
96*84943d6fSEmmanuel Vadot #define CLKID_HEVCF_P0			86
97*84943d6fSEmmanuel Vadot #define CLKID_HEVCF_P1_SEL		87
98*84943d6fSEmmanuel Vadot #define CLKID_HEVCF_P1_DIV		88
99*84943d6fSEmmanuel Vadot #define CLKID_HEVCF_P1			89
100*84943d6fSEmmanuel Vadot #define CLKID_HEVCF_SEL			90
101*84943d6fSEmmanuel Vadot #define CLKID_VPU_0_SEL			91
102*84943d6fSEmmanuel Vadot #define CLKID_VPU_0_DIV			92
103*84943d6fSEmmanuel Vadot #define CLKID_VPU_0			93
104*84943d6fSEmmanuel Vadot #define CLKID_VPU_1_SEL			94
105*84943d6fSEmmanuel Vadot #define CLKID_VPU_1_DIV			95
106*84943d6fSEmmanuel Vadot #define CLKID_VPU_1			96
107*84943d6fSEmmanuel Vadot #define CLKID_VPU			97
108*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKB_TMP_SEL		98
109*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKB_TMP_DIV		99
110*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKB_TMP		100
111*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKB_DIV		101
112*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKB			102
113*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKC_P0_SEL		103
114*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKC_P0_DIV		104
115*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKC_P0		105
116*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKC_P1_SEL		106
117*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKC_P1_DIV		107
118*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKC_P1		108
119*84943d6fSEmmanuel Vadot #define CLKID_VPU_CLKC_SEL		109
120*84943d6fSEmmanuel Vadot #define CLKID_VAPB_0_SEL		110
121*84943d6fSEmmanuel Vadot #define CLKID_VAPB_0_DIV		111
122*84943d6fSEmmanuel Vadot #define CLKID_VAPB_0			112
123*84943d6fSEmmanuel Vadot #define CLKID_VAPB_1_SEL		113
124*84943d6fSEmmanuel Vadot #define CLKID_VAPB_1_DIV		114
125*84943d6fSEmmanuel Vadot #define CLKID_VAPB_1			115
126*84943d6fSEmmanuel Vadot #define CLKID_VAPB			116
127*84943d6fSEmmanuel Vadot #define CLKID_GE2D			117
128*84943d6fSEmmanuel Vadot #define CLKID_VDIN_MEAS_SEL		118
129*84943d6fSEmmanuel Vadot #define CLKID_VDIN_MEAS_DIV		119
130*84943d6fSEmmanuel Vadot #define CLKID_VDIN_MEAS			120
131*84943d6fSEmmanuel Vadot #define CLKID_SD_EMMC_C_CLK_SEL		121
132*84943d6fSEmmanuel Vadot #define CLKID_SD_EMMC_C_CLK_DIV		122
133*84943d6fSEmmanuel Vadot #define CLKID_SD_EMMC_C			123
134*84943d6fSEmmanuel Vadot #define CLKID_SD_EMMC_A_CLK_SEL		124
135*84943d6fSEmmanuel Vadot #define CLKID_SD_EMMC_A_CLK_DIV		125
136*84943d6fSEmmanuel Vadot #define CLKID_SD_EMMC_A			126
137*84943d6fSEmmanuel Vadot #define CLKID_SD_EMMC_B_CLK_SEL		127
138*84943d6fSEmmanuel Vadot #define CLKID_SD_EMMC_B_CLK_DIV		128
139*84943d6fSEmmanuel Vadot #define CLKID_SD_EMMC_B			129
140*84943d6fSEmmanuel Vadot #define CLKID_SPICC0_SEL		130
141*84943d6fSEmmanuel Vadot #define CLKID_SPICC0_DIV		131
142*84943d6fSEmmanuel Vadot #define CLKID_SPICC0_EN			132
143*84943d6fSEmmanuel Vadot #define CLKID_PWM_A_SEL			133
144*84943d6fSEmmanuel Vadot #define CLKID_PWM_A_DIV			134
145*84943d6fSEmmanuel Vadot #define CLKID_PWM_A			135
146*84943d6fSEmmanuel Vadot #define CLKID_PWM_B_SEL			136
147*84943d6fSEmmanuel Vadot #define CLKID_PWM_B_DIV			137
148*84943d6fSEmmanuel Vadot #define CLKID_PWM_B			138
149*84943d6fSEmmanuel Vadot #define CLKID_PWM_C_SEL			139
150*84943d6fSEmmanuel Vadot #define CLKID_PWM_C_DIV			140
151*84943d6fSEmmanuel Vadot #define CLKID_PWM_C			141
152*84943d6fSEmmanuel Vadot #define CLKID_PWM_D_SEL			142
153*84943d6fSEmmanuel Vadot #define CLKID_PWM_D_DIV			143
154*84943d6fSEmmanuel Vadot #define CLKID_PWM_D			144
155*84943d6fSEmmanuel Vadot #define CLKID_PWM_E_SEL			145
156*84943d6fSEmmanuel Vadot #define CLKID_PWM_E_DIV			146
157*84943d6fSEmmanuel Vadot #define CLKID_PWM_E			147
158*84943d6fSEmmanuel Vadot #define CLKID_PWM_F_SEL			148
159*84943d6fSEmmanuel Vadot #define CLKID_PWM_F_DIV			149
160*84943d6fSEmmanuel Vadot #define CLKID_PWM_F			150
161*84943d6fSEmmanuel Vadot #define CLKID_PWM_G_SEL			151
162*84943d6fSEmmanuel Vadot #define CLKID_PWM_G_DIV			152
163*84943d6fSEmmanuel Vadot #define CLKID_PWM_G			153
164*84943d6fSEmmanuel Vadot #define CLKID_PWM_H_SEL			154
165*84943d6fSEmmanuel Vadot #define CLKID_PWM_H_DIV			155
166*84943d6fSEmmanuel Vadot #define CLKID_PWM_H			156
167*84943d6fSEmmanuel Vadot #define CLKID_PWM_I_SEL			157
168*84943d6fSEmmanuel Vadot #define CLKID_PWM_I_DIV			158
169*84943d6fSEmmanuel Vadot #define CLKID_PWM_I			159
170*84943d6fSEmmanuel Vadot #define CLKID_PWM_J_SEL			160
171*84943d6fSEmmanuel Vadot #define CLKID_PWM_J_DIV			161
172*84943d6fSEmmanuel Vadot #define CLKID_PWM_J			162
173*84943d6fSEmmanuel Vadot #define CLKID_SARADC_SEL		163
174*84943d6fSEmmanuel Vadot #define CLKID_SARADC_DIV		164
175*84943d6fSEmmanuel Vadot #define CLKID_SARADC			165
176*84943d6fSEmmanuel Vadot #define CLKID_GEN_SEL			166
177*84943d6fSEmmanuel Vadot #define CLKID_GEN_DIV			167
178*84943d6fSEmmanuel Vadot #define CLKID_GEN			168
179*84943d6fSEmmanuel Vadot #define CLKID_DDR			169
180*84943d6fSEmmanuel Vadot #define CLKID_DOS			170
181*84943d6fSEmmanuel Vadot #define CLKID_ETHPHY			171
182*84943d6fSEmmanuel Vadot #define CLKID_MALI			172
183*84943d6fSEmmanuel Vadot #define CLKID_AOCPU			173
184*84943d6fSEmmanuel Vadot #define CLKID_AUCPU			174
185*84943d6fSEmmanuel Vadot #define CLKID_CEC			175
186*84943d6fSEmmanuel Vadot #define CLKID_SDEMMC_A			176
187*84943d6fSEmmanuel Vadot #define CLKID_SDEMMC_B			177
188*84943d6fSEmmanuel Vadot #define CLKID_NAND			178
189*84943d6fSEmmanuel Vadot #define CLKID_SMARTCARD			179
190*84943d6fSEmmanuel Vadot #define CLKID_ACODEC			180
191*84943d6fSEmmanuel Vadot #define CLKID_SPIFC			181
192*84943d6fSEmmanuel Vadot #define CLKID_MSR			182
193*84943d6fSEmmanuel Vadot #define CLKID_IR_CTRL			183
194*84943d6fSEmmanuel Vadot #define CLKID_AUDIO			184
195*84943d6fSEmmanuel Vadot #define CLKID_ETH			185
196*84943d6fSEmmanuel Vadot #define CLKID_UART_A			186
197*84943d6fSEmmanuel Vadot #define CLKID_UART_B			187
198*84943d6fSEmmanuel Vadot #define CLKID_UART_C			188
199*84943d6fSEmmanuel Vadot #define CLKID_UART_D			189
200*84943d6fSEmmanuel Vadot #define CLKID_UART_E			190
201*84943d6fSEmmanuel Vadot #define CLKID_AIFIFO			191
202*84943d6fSEmmanuel Vadot #define CLKID_TS_DDR			192
203*84943d6fSEmmanuel Vadot #define CLKID_TS_PLL			193
204*84943d6fSEmmanuel Vadot #define CLKID_G2D			194
205*84943d6fSEmmanuel Vadot #define CLKID_SPICC0			195
206*84943d6fSEmmanuel Vadot #define CLKID_SPICC1			196
207*84943d6fSEmmanuel Vadot #define CLKID_USB			197
208*84943d6fSEmmanuel Vadot #define CLKID_I2C_M_A			198
209*84943d6fSEmmanuel Vadot #define CLKID_I2C_M_B			199
210*84943d6fSEmmanuel Vadot #define CLKID_I2C_M_C			200
211*84943d6fSEmmanuel Vadot #define CLKID_I2C_M_D			201
212*84943d6fSEmmanuel Vadot #define CLKID_I2C_M_E			202
213*84943d6fSEmmanuel Vadot #define CLKID_HDMITX_APB		203
214*84943d6fSEmmanuel Vadot #define CLKID_I2C_S_A			204
215*84943d6fSEmmanuel Vadot #define CLKID_USB1_TO_DDR		205
216*84943d6fSEmmanuel Vadot #define CLKID_HDCP22			206
217*84943d6fSEmmanuel Vadot #define CLKID_MMC_APB			207
218*84943d6fSEmmanuel Vadot #define CLKID_RSA			208
219*84943d6fSEmmanuel Vadot #define CLKID_CPU_DEBUG			209
220*84943d6fSEmmanuel Vadot #define CLKID_VPU_INTR			210
221*84943d6fSEmmanuel Vadot #define CLKID_DEMOD			211
222*84943d6fSEmmanuel Vadot #define CLKID_SAR_ADC			212
223*84943d6fSEmmanuel Vadot #define CLKID_GIC			213
224*84943d6fSEmmanuel Vadot #define CLKID_PWM_AB			214
225*84943d6fSEmmanuel Vadot #define CLKID_PWM_CD			215
226*84943d6fSEmmanuel Vadot #define CLKID_PWM_EF			216
227*84943d6fSEmmanuel Vadot #define CLKID_PWM_GH			217
228*84943d6fSEmmanuel Vadot #define CLKID_PWM_IJ			218
229*84943d6fSEmmanuel Vadot #define CLKID_HDCP22_ESMCLK_SEL		219
230*84943d6fSEmmanuel Vadot #define CLKID_HDCP22_ESMCLK_DIV		220
231*84943d6fSEmmanuel Vadot #define CLKID_HDCP22_ESMCLK		221
232*84943d6fSEmmanuel Vadot #define CLKID_HDCP22_SKPCLK_SEL		222
233*84943d6fSEmmanuel Vadot #define CLKID_HDCP22_SKPCLK_DIV		223
234*84943d6fSEmmanuel Vadot #define CLKID_HDCP22_SKPCLK		224
235*84943d6fSEmmanuel Vadot 
236*84943d6fSEmmanuel Vadot #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */
237