1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: StarFive Watchdog for JH7100 and JH7110 SoC 8 9maintainers: 10 - Xingyu Wu <xingyu.wu@starfivetech.com> 11 - Samin Guo <samin.guo@starfivetech.com> 12 13description: 14 The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog 15 has only one timeout phase and reboots. And JH7110 watchdog has two 16 timeout phases. At the first phase, the signal of watchdog interrupt 17 output(WDOGINT) will rise when counter is 0. The counter will reload 18 the timeout value. And then, if counter decreases to 0 again and WDOGINT 19 isn't cleared, the watchdog will reset the system unless the watchdog 20 reset is disabled. 21 22allOf: 23 - $ref: watchdog.yaml# 24 25properties: 26 compatible: 27 enum: 28 - starfive,jh7100-wdt 29 - starfive,jh7110-wdt 30 31 reg: 32 maxItems: 1 33 34 interrupts: 35 maxItems: 1 36 37 clocks: 38 items: 39 - description: APB clock 40 - description: Core clock 41 42 clock-names: 43 items: 44 - const: apb 45 - const: core 46 47 resets: 48 items: 49 - description: APB reset 50 - description: Core reset 51 52required: 53 - compatible 54 - reg 55 - clocks 56 - clock-names 57 - resets 58 59unevaluatedProperties: false 60 61examples: 62 - | 63 watchdog@12480000 { 64 compatible = "starfive,jh7100-wdt"; 65 reg = <0x12480000 0x10000>; 66 clocks = <&clk 171>, 67 <&clk 172>; 68 clock-names = "apb", "core"; 69 resets = <&rst 99>, 70 <&rst 100>; 71 }; 72