xref: /freebsd/sys/contrib/device-tree/Bindings/watchdog/qcom-wdt.yaml (revision 1719886f6d08408b834d270c59ffcfd821c8f63a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
8
9maintainers:
10  - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
11
12properties:
13  $nodename:
14    pattern: "^(watchdog|timer)@[0-9a-f]+$"
15
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qcom,kpss-wdt-ipq4019
21              - qcom,apss-wdt-ipq5332
22              - qcom,apss-wdt-ipq9574
23              - qcom,apss-wdt-msm8994
24              - qcom,apss-wdt-qcm2290
25              - qcom,apss-wdt-qcs404
26              - qcom,apss-wdt-sa8775p
27              - qcom,apss-wdt-sc7180
28              - qcom,apss-wdt-sc7280
29              - qcom,apss-wdt-sc8180x
30              - qcom,apss-wdt-sc8280xp
31              - qcom,apss-wdt-sdm845
32              - qcom,apss-wdt-sdx55
33              - qcom,apss-wdt-sdx65
34              - qcom,apss-wdt-sm6115
35              - qcom,apss-wdt-sm6350
36              - qcom,apss-wdt-sm8150
37              - qcom,apss-wdt-sm8250
38          - const: qcom,kpss-wdt
39      - const: qcom,kpss-wdt
40        deprecated: true
41      - items:
42          - const: qcom,scss-timer
43          - const: qcom,msm-timer
44      - items:
45          - enum:
46              - qcom,kpss-wdt-apq8064
47              - qcom,kpss-wdt-ipq8064
48              - qcom,kpss-wdt-mdm9615
49              - qcom,kpss-wdt-msm8960
50          - const: qcom,kpss-timer
51          - const: qcom,msm-timer
52
53  reg:
54    maxItems: 1
55
56  clocks:
57    maxItems: 1
58
59  clock-names:
60    items:
61      - const: sleep
62
63  clock-frequency:
64    description:
65      The frequency of the general purpose timer in Hz.
66
67  cpu-offset:
68    $ref: /schemas/types.yaml#/definitions/uint32
69    description:
70      Per-CPU offset used when the timer is accessed without the CPU remapping
71      facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
72
73  interrupts:
74    minItems: 1
75    maxItems: 5
76
77required:
78  - compatible
79  - reg
80  - clocks
81
82allOf:
83  - $ref: watchdog.yaml#
84
85  - if:
86      properties:
87        compatible:
88          contains:
89            const: qcom,kpss-wdt
90    then:
91      properties:
92        clock-frequency: false
93        cpu-offset: false
94        interrupts:
95          minItems: 1
96          items:
97            - description: Bark
98            - description: Bite
99
100    else:
101      properties:
102        interrupts:
103          minItems: 3
104          items:
105            - description: Debug
106            - description: First general purpose timer
107            - description: Second general purpose timer
108            - description: First watchdog
109            - description: Second watchdog
110      required:
111        - clock-frequency
112
113unevaluatedProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118
119    watchdog@17c10000 {
120        compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
121        reg = <0x17c10000 0x1000>;
122        clocks = <&sleep_clk>;
123        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
124        timeout-sec = <10>;
125    };
126
127  - |
128    #include <dt-bindings/interrupt-controller/arm-gic.h>
129
130    watchdog@200a000 {
131        compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
132        interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
133                     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
134                     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
135                     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
136                     <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
137        reg = <0x0200a000 0x100>;
138        clock-frequency = <25000000>;
139        clocks = <&sleep_clk>;
140        clock-names = "sleep";
141        cpu-offset = <0x80000>;
142    };
143