xref: /freebsd/sys/contrib/device-tree/Bindings/usb/ti,j721e-usb.yaml (revision c7046f76c2c027b00c0e6ba57cfd28f1a78f5e23) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
8
9maintainers:
10  - Roger Quadros <rogerq@kernel.org>
11
12properties:
13  compatible:
14    oneOf:
15      - const: ti,j721e-usb
16      - const: ti,am64-usb
17      - items:
18          - const: ti,j721e-usb
19          - const: ti,am64-usb
20
21  reg:
22    maxItems: 1
23
24  ranges: true
25
26  power-domains:
27    description:
28      PM domain provider node and an args specifier containing
29      the USB device id value. See,
30      Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
31    maxItems: 1
32
33  clocks:
34    description: Clock phandles to usb2_refclk and lpm_clk
35    minItems: 2
36    maxItems: 2
37
38  clock-names:
39    items:
40      - const: ref
41      - const: lpm
42
43  ti,usb2-only:
44    description:
45      If present, it restricts the controller to USB2.0 mode of
46      operation. Must be present if USB3 PHY is not available
47      for USB.
48    type: boolean
49
50  ti,vbus-divider:
51    description:
52      Should be present if USB VBUS line is connected to the
53      VBUS pin of the SoC via a 1/3 voltage divider.
54    type: boolean
55
56  assigned-clocks:
57    maxItems: 1
58
59  assigned-clock-parents:
60    maxItems: 1
61
62  '#address-cells':
63    const: 2
64
65  '#size-cells':
66    const: 2
67
68  dma-coherent: true
69
70patternProperties:
71  "^usb@":
72    type: object
73
74required:
75  - compatible
76  - reg
77  - power-domains
78  - clocks
79  - clock-names
80
81additionalProperties: false
82
83examples:
84  - |
85    #include <dt-bindings/soc/ti,sci_pm_domain.h>
86    #include <dt-bindings/interrupt-controller/arm-gic.h>
87
88    bus {
89        #address-cells = <2>;
90        #size-cells = <2>;
91
92        cdns_usb@4104000 {
93            compatible = "ti,j721e-usb";
94            reg = <0x00 0x4104000 0x00 0x100>;
95            power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
96            clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
97            clock-names = "ref", "lpm";
98            assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
99            assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
100            #address-cells = <2>;
101            #size-cells = <2>;
102
103            usb@6000000 {
104                  compatible = "cdns,usb3";
105                  reg = <0x00 0x6000000 0x00 0x10000>,
106                        <0x00 0x6010000 0x00 0x10000>,
107                        <0x00 0x6020000 0x00 0x10000>;
108                  reg-names = "otg", "xhci", "dev";
109                  interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
110                               <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
111                               <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
112                  interrupt-names = "host",
113                                    "peripheral",
114                                    "otg";
115                  maximum-speed = "super-speed";
116                  dr_mode = "otg";
117            };
118        };
119    };
120