xref: /freebsd/sys/contrib/device-tree/Bindings/usb/ti,j721e-usb.yaml (revision 25ecdc7d52770caf1c9b44b5ec11f468f6b636f3) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller
8
9maintainers:
10  - Roger Quadros <rogerq@ti.com>
11
12properties:
13  compatible:
14    items:
15      - const: ti,j721e-usb
16
17  reg:
18    description: module registers
19
20  power-domains:
21    description:
22      PM domain provider node and an args specifier containing
23      the USB device id value. See,
24      Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
25
26  clocks:
27    description: Clock phandles to usb2_refclk and lpm_clk
28    minItems: 2
29    maxItems: 2
30
31  clock-names:
32    items:
33      - const: ref
34      - const: lpm
35
36  ti,usb2-only:
37    description:
38      If present, it restricts the controller to USB2.0 mode of
39      operation. Must be present if USB3 PHY is not available
40      for USB.
41    type: boolean
42
43  ti,vbus-divider:
44    description:
45      Should be present if USB VBUS line is connected to the
46      VBUS pin of the SoC via a 1/3 voltage divider.
47    type: boolean
48
49  assigned-clocks:
50    maxItems: 1
51
52  assigned-clock-parents:
53    maxItems: 1
54
55  '#address-cells':
56    const: 2
57
58  '#size-cells':
59    const: 2
60
61patternProperties:
62  "^usb@":
63    type: object
64
65required:
66  - compatible
67  - reg
68  - power-domains
69  - clocks
70  - clock-names
71
72additionalProperties: false
73
74examples:
75  - |
76    #include <dt-bindings/soc/ti,sci_pm_domain.h>
77    #include <dt-bindings/interrupt-controller/arm-gic.h>
78
79    bus {
80        #address-cells = <2>;
81        #size-cells = <2>;
82
83        cdns_usb@4104000 {
84            compatible = "ti,j721e-usb";
85            reg = <0x00 0x4104000 0x00 0x100>;
86            power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
87            clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
88            clock-names = "ref", "lpm";
89            assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
90            assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
91            #address-cells = <2>;
92            #size-cells = <2>;
93
94            usb@6000000 {
95                  compatible = "cdns,usb3";
96                  reg = <0x00 0x6000000 0x00 0x10000>,
97                        <0x00 0x6010000 0x00 0x10000>,
98                        <0x00 0x6020000 0x00 0x10000>;
99                  reg-names = "otg", "xhci", "dev";
100                  interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
101                               <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
102                               <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
103                  interrupt-names = "host",
104                                    "peripheral",
105                                    "otg";
106                  maximum-speed = "super-speed";
107                  dr_mode = "otg";
108            };
109        };
110    };
111