xref: /freebsd/sys/contrib/device-tree/Bindings/usb/snps,dwc3.yaml (revision 5def4c47d4bd90b209b9b4a4ba9faec15846d8fd) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare USB3 Controller
8
9maintainers:
10  - Felipe Balbi <balbi@kernel.org>
11
12description:
13  This is usually a subnode to DWC3 glue to which it is connected, but can also
14  be presented as a standalone DT node with an optional vendor-specific
15  compatible string.
16
17allOf:
18  - $ref: usb-drd.yaml#
19  - if:
20      properties:
21        dr_mode:
22          const: peripheral
23
24      required:
25        - dr_mode
26    then:
27      $ref: usb.yaml#
28    else:
29      $ref: usb-xhci.yaml#
30
31properties:
32  compatible:
33    contains:
34      oneOf:
35        - const: snps,dwc3
36        - const: synopsys,dwc3
37          deprecated: true
38
39  interrupts:
40    description:
41      It's either a single common DWC3 interrupt (dwc_usb3) or individual
42      interrupts for the host, gadget and DRD modes.
43    minItems: 1
44    maxItems: 3
45
46  interrupt-names:
47    minItems: 1
48    maxItems: 3
49    oneOf:
50      - const: dwc_usb3
51      - items:
52          enum: [host, peripheral, otg]
53
54  clocks:
55    description:
56      In general the core supports three types of clocks. bus_early is a
57      SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
58      PHY is suspended. suspend clocks a small part of the USB3 core when
59      SS PHY in P3. But particular cases may differ from that having less
60      or more clock sources with another names.
61
62  clock-names:
63    contains:
64      anyOf:
65        - enum: [bus_early, ref, suspend]
66        - true
67
68  usb-phy:
69    minItems: 1
70    items:
71      - description: USB2/HS PHY
72      - description: USB3/SS PHY
73
74  phys:
75    minItems: 1
76    items:
77      - description: USB2/HS PHY
78      - description: USB3/SS PHY
79
80  phy-names:
81    minItems: 1
82    items:
83      - const: usb2-phy
84      - const: usb3-phy
85
86  resets:
87    minItems: 1
88
89  snps,usb2-lpm-disable:
90    description: Indicate if we don't want to enable USB2 HW LPM
91    type: boolean
92
93  snps,usb3_lpm_capable:
94    description: Determines if platform is USB3 LPM capable
95    type: boolean
96
97  snps,dis-start-transfer-quirk:
98    description:
99      When set, disable isoc START TRANSFER command failure SW work-around
100      for DWC_usb31 version 1.70a-ea06 and prior.
101    type: boolean
102
103  snps,disable_scramble_quirk:
104    description:
105      True when SW should disable data scrambling. Only really useful for FPGA
106      builds.
107    type: boolean
108
109  snps,has-lpm-erratum:
110    description: True when DWC3 was configured with LPM Erratum enabled
111    type: boolean
112
113  snps,lpm-nyet-threshold:
114    description: LPM NYET threshold
115    $ref: /schemas/types.yaml#/definitions/uint8
116
117  snps,u2exit_lfps_quirk:
118    description: Set if we want to enable u2exit lfps quirk
119    type: boolean
120
121  snps,u2ss_inp3_quirk:
122    description: Set if we enable P3 OK for U2/SS Inactive quirk
123    type: boolean
124
125  snps,req_p1p2p3_quirk:
126    description:
127      When set, the core will always request for P1/P2/P3 transition sequence.
128    type: boolean
129
130  snps,del_p1p2p3_quirk:
131    description:
132      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
133      occur.
134    type: boolean
135
136  snps,del_phy_power_chg_quirk:
137    description: When set core will delay PHY power change from P0 to P1/P2/P3.
138    type: boolean
139
140  snps,lfps_filter_quirk:
141    description: When set core will filter LFPS reception.
142    type: boolean
143
144  snps,rx_detect_poll_quirk:
145    description:
146      when set core will disable a 400us delay to start Polling LFPS after
147      RX.Detect.
148    type: boolean
149
150  snps,tx_de_emphasis_quirk:
151    description: When set core will set Tx de-emphasis value
152    type: boolean
153
154  snps,tx_de_emphasis:
155    description:
156      The value driven to the PHY is controlled by the LTSSM during USB3
157      Compliance mode.
158    $ref: /schemas/types.yaml#/definitions/uint8
159    enum:
160      - 0 # -6dB de-emphasis
161      - 1 # -3.5dB de-emphasis
162      - 2 # No de-emphasis
163
164  snps,dis_u3_susphy_quirk:
165    description: When set core will disable USB3 suspend phy
166    type: boolean
167
168  snps,dis_u2_susphy_quirk:
169    description: When set core will disable USB2 suspend phy
170    type: boolean
171
172  snps,dis_enblslpm_quirk:
173    description:
174      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
175      to the PHY.
176    type: boolean
177
178  snps,dis-u1-entry-quirk:
179    description: Set if link entering into U1 needs to be disabled
180    type: boolean
181
182  snps,dis-u2-entry-quirk:
183    description: Set if link entering into U2 needs to be disabled
184    type: boolean
185
186  snps,dis_rxdet_inp3_quirk:
187    description:
188      When set core will disable receiver detection in PHY P3 power state.
189    type: boolean
190
191  snps,dis-u2-freeclk-exists-quirk:
192    description:
193      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
194      PHY doesn't provide a free-running PHY clock.
195    type: boolean
196
197  snps,dis-del-phy-power-chg-quirk:
198    description:
199      When set core will change PHY power from P0 to P1/P2/P3 without delay.
200    type: boolean
201
202  snps,dis-tx-ipgap-linecheck-quirk:
203    description: When set, disable u2mac linestate check during HS transmit
204    type: boolean
205
206  snps,parkmode-disable-ss-quirk:
207    description:
208      When set, all SuperSpeed bus instances in park mode are disabled.
209    type: boolean
210
211  snps,dis_metastability_quirk:
212    description:
213      When set, disable metastability workaround. CAUTION! Use only if you are
214      absolutely sure of it.
215    type: boolean
216
217  snps,dis-split-quirk:
218    description:
219      When set, change the way URBs are handled by the driver. Needed to
220      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
221    type: boolean
222
223  snps,is-utmi-l1-suspend:
224    description:
225      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
226      asserts utmi_sleep_n.
227    type: boolean
228
229  snps,hird-threshold:
230    description: HIRD threshold
231    $ref: /schemas/types.yaml#/definitions/uint8
232
233  snps,hsphy_interface:
234    description:
235      High-Speed PHY interface selection between UTMI+ and ULPI when the
236      DWC_USB3_HSPHY_INTERFACE has value 3.
237    $ref: /schemas/types.yaml#/definitions/uint8
238    enum: [utmi, ulpi]
239
240  snps,quirk-frame-length-adjustment:
241    description:
242      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
243      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
244      incorrect.
245    $ref: /schemas/types.yaml#/definitions/uint32
246    minimum: 0
247    maximum: 0x3f
248
249  snps,rx-thr-num-pkt-prd:
250    description:
251      Periodic ESS RX packet threshold count (host mode only). Set this and
252      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
253      programming guide section 1.2.4) to enable periodic ESS RX threshold.
254    $ref: /schemas/types.yaml#/definitions/uint8
255    minimum: 1
256    maximum: 16
257
258  snps,rx-max-burst-prd:
259    description:
260      Max periodic ESS RX burst size (host mode only). Set this and
261      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
262      programming guide section 1.2.4) to enable periodic ESS RX threshold.
263    $ref: /schemas/types.yaml#/definitions/uint8
264    minimum: 1
265    maximum: 16
266
267  snps,tx-thr-num-pkt-prd:
268    description:
269      Periodic ESS TX packet threshold count (host mode only). Set this and
270      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
271      programming guide section 1.2.3) to enable periodic ESS TX threshold.
272    $ref: /schemas/types.yaml#/definitions/uint8
273    minimum: 1
274    maximum: 16
275
276  snps,tx-max-burst-prd:
277    description:
278      Max periodic ESS TX burst size (host mode only). Set this and
279      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
280      programming guide section 1.2.3) to enable periodic ESS TX threshold.
281    $ref: /schemas/types.yaml#/definitions/uint8
282    minimum: 1
283    maximum: 16
284
285  tx-fifo-resize:
286    description: Determines if the FIFO *has* to be reallocated
287    deprecated: true
288    type: boolean
289
290  snps,incr-burst-type-adjustment:
291    description:
292      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
293      burst type enable and INCRx type. A single value means INCRX burst mode
294      enabled. If more than one value specified, undefined length INCR burst
295      type will be enabled with burst lengths utilized up to the maximum
296      of the values passed in this property.
297    $ref: /schemas/types.yaml#/definitions/uint32-array
298    minItems: 1
299    maxItems: 8
300    uniqueItems: true
301    items:
302      enum: [1, 4, 8, 16, 32, 64, 128, 256]
303
304unevaluatedProperties: false
305
306required:
307  - compatible
308  - reg
309  - interrupts
310
311examples:
312  - |
313    usb@4a030000 {
314      compatible = "snps,dwc3";
315      reg = <0x4a030000 0xcfff>;
316      interrupts = <0 92 4>;
317      usb-phy = <&usb2_phy>, <&usb3_phy>;
318      snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
319    };
320  - |
321    usb@4a000000 {
322      compatible = "snps,dwc3";
323      reg = <0x4a000000 0xcfff>;
324      interrupts = <0 92 4>;
325      clocks = <&clk 1>, <&clk 2>, <&clk 3>;
326      clock-names = "bus_early", "ref", "suspend";
327      phys = <&usb2_phy>, <&usb3_phy>;
328      phy-names = "usb2-phy", "usb3-phy";
329      snps,dis_u2_susphy_quirk;
330      snps,dis_enblslpm_quirk;
331    };
332...
333