1Rockchip SuperSpeed DWC3 USB SoC controller 2 3Required properties: 4- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC 5- clocks: A list of phandle + clock-specifier pairs for the 6 clocks listed in clock-names 7- clock-names: Should contain the following: 8 "ref_clk" Controller reference clk, have to be 24 MHz 9 "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz 10 "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS 11 operation and >= 30MHz for HS operation 12 "grf_clk" Controller grf clk 13 14Required child node: 15A child node must exist to represent the core DWC3 IP block. The name of 16the node is not important. The content of the node is defined in dwc3.txt. 17 18Phy documentation is provided in the following places: 19Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY 20Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY 21 22Example device nodes: 23 24 usbdrd3_0: usb@fe800000 { 25 compatible = "rockchip,rk3399-dwc3"; 26 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 27 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; 28 clock-names = "ref_clk", "suspend_clk", 29 "bus_clk", "grf_clk"; 30 #address-cells = <2>; 31 #size-cells = <2>; 32 ranges; 33 usbdrd_dwc3_0: dwc3@fe800000 { 34 compatible = "snps,dwc3"; 35 reg = <0x0 0xfe800000 0x0 0x100000>; 36 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 37 dr_mode = "otg"; 38 }; 39 }; 40 41 usbdrd3_1: usb@fe900000 { 42 compatible = "rockchip,rk3399-dwc3"; 43 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 44 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; 45 clock-names = "ref_clk", "suspend_clk", 46 "bus_clk", "grf_clk"; 47 #address-cells = <2>; 48 #size-cells = <2>; 49 ranges; 50 usbdrd_dwc3_1: dwc3@fe900000 { 51 compatible = "snps,dwc3"; 52 reg = <0x0 0xfe900000 0x0 0x100000>; 53 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 54 dr_mode = "otg"; 55 }; 56 }; 57